3D Memory Cell Layout With Staggered Stacks and Shared Lines
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Solution Overview
Problem
The semiconductor industry faces challenges in simplifying the fabrication process and reducing costs as feature sizes decrease, particularly in the alignment and connection of source and drain regions in 3D memory structures, which complicates the formation of circuit components and increases complexity.
Innovation Solution
The proposed solution involves a 3D memory structure with vertically stacked memory cells, where the arrangement of memory cells and the routing/connections of the source line and bit line arrays are adjusted to simplify the process flow, using a staggered layout and shared word lines and source/bit lines to reduce the number of photomasks and fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional alignment and connection methods are used for source and drain regions in 3D memory structures, then manufacturing precision can be maintained, but device complexity and fabrication process complexity increase significantly
Solution Approach 1:
The patent employs asymmetric offset alignment between source and drain regions in vertically stacked memory cells. Instead of aligning source and drain regions directly above each other, they are positioned with a lateral offset, creating an asymmetric configuration that simplifies the fabrication process by reducing alignment constraints while maintaining functional performance
Solution Approach 2:
The patent transitions from two-dimensional planar alignment to three-dimensional offset alignment. By utilizing the lateral dimension in addition to vertical stacking, the design creates staggered source and drain regions that are offset in the lateral direction, thereby reducing alignment complexity without compromising manufacturing precision
2Productivity
If more photomasks and fabrication steps are used, then manufacturing precision can be improved, but productivity decreases and costs increase
Solution Approach 1:
The patent merges multiple alignment operations into a single photomask step by designing the staggered source and drain regions to be formed simultaneously. This consolidation reduces the total number of photomasks required while maintaining the necessary pattern alignment precision through the offset geometry design
Solution Approach 2:
The offset alignment design serves multiple functions: it simplifies fabrication by reducing photomask steps, maintains manufacturing precision through geometric constraints, and enables vertical stacking for higher density. This multi-functional approach improves productivity without sacrificing precision
Data Source
AI summary
A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.