3D Memory Cell Stair Contacts for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high integration density and reducing parasitic capacitance in memory devices, particularly in three-dimensional (3D) memory cell stacks.
Innovation Solution
A method for fabricating a semiconductor device involves forming a mold stack of conductive layers with a stair structure, where contact holes with gradually decreasing heights are formed, and contact plugs are coupled to the conductive layers, enabling efficient vertical stacking of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar memory structures are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from planar (2D) memory structures to three-dimensional (3D) stacked structures by vertically stacking multiple memory cell layers. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate, allowing multiple memory cells to be stacked in the third dimension while maintaining compatibility with conventional manufacturing processes
2Reliability
If taller contact holes are formed to reach lower conductive layers, then connectivity is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent segments the contact structure into multiple parts: contact holes through the stair structure, intermediate contact plugs, and upper contact holes. This segmentation allows the contact path to be divided into shorter segments that can be optimized individually, reducing the total capacitance while maintaining connectivity to lower conductive layers
Solution Approach 2:
The patent applies different local qualities to different regions of the contact structure. The stair structure provides gradual height reduction with specific etch profiles, while contact holes in upper regions have different dimensions and materials optimized for their specific function. This local optimization reduces parasitic capacitance in critical regions while maintaining overall connectivity
3Ease of manufacture
If uniform contact holes are formed throughout the stack, then manufacturing is simpler, but alignment precision to varying conductive layer heights is difficult
Solution Approach 1:
The patent forms the stair structure as a preliminary feature before forming contact holes. This pre-formed stair structure with gradually decreasing heights serves as a built-in alignment reference that guides subsequent contact hole formation processes, enabling precise alignment to varying conductive layer heights without requiring complex real-time adjustment mechanisms
Solution Approach 2:
The stair structure acts as an intermediary element between the uniform substrate and the varying heights of conductive layers. This intermediate structure provides a graduated transition that facilitates precise alignment of contact holes to different conductive layer levels, bridging the gap between simple uniform manufacturing and complex alignment requirements
Data Source
AI summary
Disclosed are a semiconductor device including highly integrated memory cells, and a method for fabricating the semiconductor device. A method for fabricating a semiconductor device includes forming a mold stack of conductive layers over a lower structure, the mold stack including a first horizontal conductive line, a second horizontal conductive line, and a pad between the first horizontal conductive line and the second horizontal conductive line; forming a vertical stack of a stair structure whose height is gradually decreased in a stack direction that the conductive layers are stacked by selectively etching a portion of the mold stack; forming contact holes in the stair structure, wherein heights of the contact holes are gradually decreased in the stack direction; and forming contact plugs in the contact holes, the contact plugs coupled to the conductive layers, respectively.