3D Memory Stair Formation With Two-Stage Sacrificial Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in forming 3D memory devices is the difficulty in controlling the etch process, which leads to voids in the sacrificial layers, resulting in thinner or disconnected conductive layers, increased resistance, and impaired device performance.
Innovation Solution
The method involves forming a stack structure with interleaved layers, creating a stair structure, and depositing a sacrificial material layer with different etch selectivity sub-layers. An anisotropic etching process is used to partially remove the sacrificial material, followed by an isotropic etching process to fully remove the unwanted portions, ensuring controlled etching and maintaining the integrity of the conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching process is used to remove sacrificial material, then the process is simpler and faster, but it causes voids in the sacrificial layers resulting in thinner or disconnected conductive layers
Solution Approach 1:
The etching process is divided into two distinct stages: a first etching process that removes sacrificial material from side surfaces while preserving top surface material, and a second etching process that completes the removal. This segmentation prevents void formation and maintains conductive layer integrity by controlling the etching sequence and direction.
Solution Approach 2:
The first etching process performs preliminary removal of sacrificial material from side surfaces before the second etching process addresses the top surface. This preliminary action prevents void formation by establishing a controlled etching sequence that maintains structural integrity throughout the process.
2Ease of manufacture
If the sacrificial material layer is completely removed early in the process, then subsequent processing is simpler, but conductive layers become thinner or disconnected increasing resistance
Solution Approach 1:
The sacrificial material is partially removed in a preliminary first etching process that targets side surfaces while intentionally preserving top surface material. This preliminary removal simplifies subsequent processing while maintaining conductive layer continuity, preventing the harmful effect of complete early removal.
Solution Approach 2:
The etching process applies different removal rates to different locations: side surface sacrificial material is removed in the first etching process, while top surface sacrificial material is preserved until the second etching process. This local differentiation maintains conductive layer integrity while enabling simplified subsequent processing.
3Manufacturing precision
If anisotropic etching is used to selectively remove side surface material, then top surface sacrificial material is preserved, but additional etching steps are required
Solution Approach 1:
The selective removal process is segmented into two etching steps: a first etching process using anisotropic etching to remove side surface sacrificial material while preserving top surface material, and a second etching process to complete the removal. This segmentation achieves precise selective removal while managing process complexity through systematic staging.
Solution Approach 2:
The first etching process performs preliminary selective removal of side surface sacrificial material using anisotropic etching, preserving top surface material for subsequent processing. This preliminary selective action reduces overall complexity by preparing the structure in a controlled intermediate state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of conductive layers with sufficient thickness to act as etch-stop layers and maintain low resistance, thereby enhancing the performance and reliability of 3D memory devices.
Implementation Method 1
partially removing the first portion of the layer of sacrificial material using an anisotropic etching process
Implementation Method 2
removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process
Data Source
AI summary
A method for forming a memory device is disclosed. A stack structure including interleaved first layers and second layers is formed. A staircase structure including stairs at an edge of the stack structure is formed. Each stair has one of the first layers on a top surface of the stair. A third layer including vertical portions covering side surface of the stairs and lateral portions covering the top surface of the stairs is formed. The third layer includes a first sublayer in contact with the stair and a second sublayer in contact with the first sublayer and on the first sublayer. A mask covering the vertical portions and the lateral portions of the third layer is formed. A portion of the mask covering the vertical portions of the third layer is removed to expose the vertical portions of the third layer. Vertical portions of the first sublayer are removed using a first etching process. Vertical portions of the second sublayer are removed using a second etching process. An etching rate of the second sublayer is higher than an etching rate of the first sublayer in the second etching process.