3D Semiconductor Memory Stair Structure Integration
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Solution Overview
Problem
Current 3D semiconductor memory devices face challenges in achieving high integration density and reliability due to defects in the stair structure formation on the connection region, which affects the stack structure's integrity and performance.
Innovation Solution
The proposed solution involves a stack structure with a stair configuration on the connection region, featuring a vertical channel structure with abrupt diameter change and a second insulating layer selectively disposed on the cell array region, along with vertical dummy structures to support the stack structure, ensuring proper alignment and integration of channel holes and dummy holes to prevent defects and enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stair structure is formed on the connection region to increase integration density, then the number of memory cells per unit area increases, but process defects occur during stair structure formation affecting reliability
Solution Approach 1:
The stack structure is divided into multiple levels (first level, second level, third level) with different configurations on the cell array region and connection region. The connection region contains fewer electrodes at higher levels, creating a segmented stair structure that reduces process complexity and defect rates while maintaining high integration density.
Solution Approach 2:
Different regions of the device have different structural configurations. The cell array region maintains full electrode stacks for maximum memory density, while the connection region has selectively reduced electrodes to simplify interconnect formation and reduce manufacturing defects. This local differentiation resolves the contradiction between density and reliability.
2Reliability
If vertical channel structures with abrupt diameter change are used to improve device performance, then switching characteristics are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
A second insulating layer is formed preliminarily on the cell array region before completing the electrode stack formation. This preliminary structure serves as a template that guides subsequent etching processes to create the abrupt diameter change in vertical channels, achieving precise diameter control through pre-established boundaries rather than direct etching control.
Solution Approach 2:
The second insulating layer acts as an intermediary structure that defines the boundary for channel diameter transitions. Instead of directly controlling the complex abrupt diameter change, the insulating layer mediates the process by providing a physical boundary that the channel structure follows, simplifying manufacturing precision requirements.
3Stability of the object's composition
If vertical dummy structures are added to support the stack structure on the connection region, then structural integrity is improved, but device complexity increases
Solution Approach 1:
The vertical dummy structures serve multiple functions: they provide mechanical support to maintain stack structure integrity on the connection region, act as placeholders for future interconnect formation, and maintain etch selectivity references during manufacturing. This multi-functionality justifies the added structural elements without proportionally increasing complexity.
Data Source
AI summary
In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.