3D Memory Device Stair-Step Conductive Strips Bandwidth
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Solution Overview
Problem
Conventional 3D memory devices face limitations in read and program operation bandwidth due to the configuration of bit lines, which affects storage capacity and efficiency.
Innovation Solution
The 3D memory device incorporates a unique arrangement of stair-step structures and conductive strips to enhance the bandwidth of read and programming operations, with conductive strips electrically connected to semiconductor strips via stair-step structures, allowing for improved access to memory cells across multiple layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit line configuration is used in 3D memory devices, then device structure is simple, but read and program operation bandwidth is limited
Solution Approach 1:
The bit lines are segmented into multiple conductive strips arranged in parallel, with each strip serving a specific memory stack. This segmentation allows simultaneous access to multiple memory locations, thereby increasing the bandwidth of read and program operations while maintaining manageable structural complexity through modular organization
Solution Approach 2:
The patent transitions from conventional two-dimensional bit line arrangement to a three-dimensional configuration where conductive strips are stacked vertically and arranged in parallel. This dimensional change enables multiple bit lines to access different memory layers simultaneously, significantly improving operation bandwidth without proportionally increasing device footprint
2Quantity of substance
If multiple planes of memory cells are arranged to achieve greater storage capacity, then storage capacity increases, but bit line configuration complexity increases affecting read and program speed
Solution Approach 1:
Each memory plane is served by dedicated conductive strips, segmenting the bit line network into independent parallel channels. This allows simultaneous read and program operations across multiple planes without interference, maintaining high speed while supporting increased storage capacity through multi-plane architecture
Solution Approach 2:
The conductive strips are designed to serve multiple functions: they act as bit lines for read operations, program operations, and erasure operations across different memory planes. This multi-functionality reduces the need for separate dedicated lines for each operation type, improving speed while managing the complexity of multi-plane configurations
Data Source
AI summary
A 3D memory device comprising a memory unit block, a first stair-step structure, a second stair-step structure, a first conductive strip and a second conductive strip is provided. The memory unit block comprises a first stacked structure comprising a first semiconductor strip and a second stacked structure comprising a second semiconductor strip. The first stair-step structure is disposed on one side of the memory unit block. The second stair-step structure is disposed on an opposite side of the memory unit block. The first conductive strip electrically coupled to the first semiconductor strip via the first stair-step structure. The second conductive strip electrically coupled to the second semiconductor strip via the second stair-step structure.