3D Memory Interconnections Stair Step Structure
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Solution Overview
Problem
The scaling of 3D NAND memory is limited due to capacitive coupling and challenges in transitioning interconnections as the number of conductive lines increases, making it difficult to maintain effective interconnections within the constrained width of the conductive line stack.
Innovation Solution
The implementation of a stair step structure in the stack of materials for 3D memory, where each stair step includes a pair of materials with a conductive line over insulation, allows for perpendicular interconnections that extend beyond the narrow width portion, thereby increasing the number of stair steps and relaxing the pitch constraint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of conductive lines in the stack is increased to improve memory capacity, then the memory density is improved, but the capacitive coupling between adjacent conductive lines increases and the interconnection transition becomes more difficult
Solution Approach 1:
The patent introduces a stair step structure that extends interconnections in a lateral direction beyond the narrow width portion of the stack. This adds a dimensional component to the interconnection path, allowing conductive lines to be accessed from the side rather than only from the top, thereby reducing capacitive coupling between adjacent lines while maintaining high memory density.
Solution Approach 2:
The stack is divided into a narrow width portion and a broad width portion, with the stair step structure creating segmented access points. This segmentation allows different regions of the stack to be accessed independently, reducing the overall capacitive coupling by separating the electrical paths of adjacent conductive lines.
2Area of stationary object
If the width of the stack is constrained to maintain device footprint, then the device area is reduced, but the number of accessible conductive lines by interconnections is limited
Solution Approach 1:
The stair step structure utilizes the lateral dimension to access conductive lines that would otherwise be inaccessible within the constrained footprint. By extending interconnections sideways from the narrow width portion, the patent effectively increases the number of accessible lines without increasing the top-down footprint of the device.
Solution Approach 2:
The stair step structure is nested within the existing stack architecture, with steps formed at the edge of the stack. This nested approach allows additional interconnection access points to be integrated into the existing structure without requiring additional lateral space, thereby maintaining a compact footprint while increasing accessibility.
3Productivity
If the pitch between interconnections is reduced to access more conductive lines, then the interconnection density is improved, but the manufacturing precision requirements increase and capacitive coupling worsens
Solution Approach 1:
By transitioning from vertical-only interconnection access to lateral-plus-vertical access via the stair step structure, the patent effectively increases the spacing between interconnection points. This dimensional change allows for relaxed pitch requirements while maintaining high interconnection density, as lines can be accessed from multiple directions rather than requiring tightly spaced vertical access points.
Data Source
AI summary
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.