3D Memory Stair-Step Layout for Wordline Isolation and Access
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Solution Overview
Problem
Existing memory array architectures face challenges in efficiently connecting memory cells in a three-dimensional arrangement, particularly in vertically-stacked configurations, which can lead to electrical shorting and hinder effective access to wordlines.
Innovation Solution
The implementation of a stair-step structure with alternating insulative and conductive tiers, along with channel openings and conductive vias, allows for direct electrical coupling of memory cells, ensuring proper isolation and access to wordlines in a vertically-stacked memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in vertically-stacked three-dimensional configuration, then storage density is improved, but electrical shorting between adjacent structures occurs
Solution Approach 1:
The structure is segmented into alternating insulative and conductive tiers, with insulative material positioned between adjacent memory cell strings to electrically isolate them while maintaining vertical stacking for high density storage
Solution Approach 2:
Insulative material acts as an intermediary layer between conductive tiers and adjacent memory cell strings, preventing direct electrical contact and shorting while allowing the vertically-stacked architecture to maintain its high storage density
2Ease of manufacture
If conventional connection structures are used in vertically-stacked memory arrays, then manufacturing is simplified, but access to wordlines is hindered
Solution Approach 1:
The structure implements local quality variations with conductive tiers positioned at specific locations to provide direct wordline access pathways, while insulative tiers are positioned elsewhere to provide isolation, creating localized functional zones that simultaneously improve access and maintain manufacturing simplicity
Data Source
AI summary
Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.