3D Memory Staircase Layout for Stress-Induced Alignment Control

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Solution Overview

Problem

The stacked structure of semiconductor memory devices experiences positional deviations among components due to stress during manufacturing, leading to operational issues and quality control challenges.

Innovation Solution

A semiconductor memory device design featuring a stacked body with alternating conductive and insulating layers, including a staircase region divided by plate-like portions and inverted staircase portions, along with pillars and plugs arranged to minimize stress-induced positional deviations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a stacked structure of conductive layers is used to increase memory capacity, then the storage density is improved, but positional deviations among components occur due to stress during manufacturing

Engineering Contradiction:
Improvestorage densityVSAvoidpositional alignment
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The stacked body is divided into multiple independent stacked layers (first stacked body, second stacked body, third stacked body) that are stacked in the vertical direction. Each stacked layer can be manufactured and positioned independently, allowing stress to be distributed and managed across separate segments rather than accumulating in a single continuous structure. This segmentation reduces the overall stress-induced positional deviation while maintaining high storage density through vertical stacking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulating layers are introduced as intermediary elements between the conductive layers in the stacked structure. These insulating layers act as stress-absorbing mediators that prevent stress transfer between adjacent conductive layers, thereby reducing positional deviations. The insulating layers provide mechanical decoupling while maintaining electrical isolation, allowing each conductive layer to maintain its positional integrity independently.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the stacked structure is manufactured with high precision to ensure component alignment, then positional deviation is reduced, but manufacturing complexity and difficulty increase

Engineering Contradiction:
Improvecomponent alignmentVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into separate steps for forming different stacked bodies (first stacked body, second stacked body, third stacked body). Each stacked body can be manufactured using standardized processes and then assembled vertically. This segmentation allows each module to be manufactured with常规 precision requirements, avoiding the need for extremely high precision across the entire stacked structure in a single manufacturing run, thereby reducing overall manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If the stacked structure is manufactured with high precision to ensure component alignment, then positional deviation is reduced, but manufacturing time and cost increase

Engineering Contradiction:
Improvecomponent alignmentVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The stacked memory structure is divided into multiple stacked bodies that can be manufactured in parallel or in a standardized sequence. Each stacked body represents a modular unit that can be produced using the same manufacturing process, enabling batch production and improving manufacturing efficiency. The segmentation allows for optimized production planning and reduces the overall manufacturing time compared to producing a single large-scale stacked structure with extremely high precision requirements.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12414298B2Semiconductor memory device
Publication Date: 2025.09.09 KIOXIA CORP
  • US12414298B2 patent drawing
  • US12414298B2 patent drawing
  • US12414298B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes a first staircase portion that is arranged in a staircase region at a position that overlaps a plate-like portion in a stacking direction, in which a plurality of conductive layers is terraced in a first direction; and a second staircase portion and a third staircase portion arranged in the staircase region on both sides in a second direction of the plate-like portion, and having structures in each of which the plurality of conductive layers is terraced, and that are mutually inverted in the second direction with respect to the plate-like portion. A plurality of first plugs is individually arranged at different positions in the second direction relative to the plate-like portion, depending on positions in the first direction, and a plurality of second plugs is individually arranged at positions inverted in the second direction from the respective positions of the plurality of first plugs, with respect to the plate-like portion.