3D Semiconductor Memory Devices With Staircase Connection Structures
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Solution Overview
Problem
Two-dimensional (2D) planar NAND semiconductor devices face limitations in capacity expansion without compromising performance and reliability, and 3D memory technology is needed to improve cell density by stacking memory cells vertically, but this approach often results in increased connection region size, leading to larger chip sizes.
Innovation Solution
A 3D semiconductor memory device with a stair structure for electrical connections between horizontal layers and peripheral circuits, allowing for a compact chip design by confining connections to a small area and using block selection gate electrodes to intersect sidewalls, enabling selective connection of memory blocks to a common contact plug.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically in 3D structure, then cell density is improved, but connection region size increases
Solution Approach 1:
The patent transitions from 2D planar connections to 3D vertical connections by stacking memory cells vertically and providing electrical connections through the stacked structure. The connection region is positioned at the top surface of the stacked memory cells, utilizing the vertical dimension to reduce the horizontal area required for connections.
Solution Approach 2:
The patent divides the memory device into distinct regions: a cell array region containing stacked memory cells, a connection region at the top surface for electrical connections, and a peripheral circuit region. This segmentation allows the connection region to be confined to a small area at the top while the bulk of the device contains the high-density stacked cells.
2Area of stationary object
If connection region size is reduced, then chip size is reduced, but electrical connection reliability may worsen
Solution Approach 1:
The patent provides different structural characteristics to different regions: the connection region at the top surface has optimized electrical connection structures with appropriate spacing and contact areas, while the stacked memory cells in the cell array region have structures optimized for high density. This local optimization maintains connection reliability while reducing overall chip size.
3Adaptability or versatility
If block selection gate electrodes intersect sidewalls of electrode portions, then selective connection capability is improved, but device complexity increases
Solution Approach 1:
The block selection gate electrodes are positioned to intersect the sidewalls of electrode portions, creating dynamically controllable selection regions. By applying voltages to these gate electrodes, the device can selectively connect or disconnect specific memory blocks from the connection region, enabling flexible and adaptive memory access patterns.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device includes a substrate including a cell array region, a connection region, and a block selection region between the cell array and connection regions, a stack structure including horizontal layers vertically stacked on the substrate, each of the horizontal layers including electrode portions extending in a first direction on the cell array and block selection regions and a connecting portion disposed on the connection region to connect the electrode portions in a second direction perpendicular to the first direction, and block selection gate electrodes intersecting sidewalls of the electrode portions of the horizontal layers on the block selection region. Each of the electrode portions includes a first semiconductor region having a first conductivity type on the cell array region and includes a channel dopant region having a second conductivity type different from the first conductivity type on the block selection region.