3D Memory Staircase and Contact Structures for Density Scaling
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, leading to density constraints, which can be addressed by transitioning to a three-dimensional memory architecture.
Innovation Solution
A three-dimensional memory device is formed with through-substrate-trenches and a film stack of alternating conductive and dielectric layers, featuring a staircase structure and contact structures on opposite sides of the substrate, allowing for increased storage density and reduced manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is pursued, then storage density is improved, but feature size approaches lower limit and fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking multiple layers of memory cells vertically. This dimensional change allows continued increase in storage density without further reduction in planar feature sizes, thereby avoiding the manufacturing precision challenges and costs associated with extreme scaling.
2Quantity of substance
If planar memory cell scaling is pursued, then storage density is improved, but fabrication costs increase
Solution Approach 1:
By moving to 3D stacked architecture, the patent achieves higher storage density through vertical stacking rather than continuous planar scaling. This approach uses more conventional fabrication processes for the planar dimensions while adding vertical complexity, thereby avoiding the exponentially increasing costs associated with pushing planar feature sizes to their physical limits.
3Manufacturing precision
If contact structures are formed with strict ground rules, then manufacturing precision is improved, but parasitic resistance increases
Solution Approach 1:
The patent forms contact structures that extend through the substrate in the vertical dimension, creating through-substrate contacts. This vertical approach allows contact structures to reach underlying layers without requiring extremely small lateral dimensions, thereby maintaining manufacturing precision while reducing the lateral path length and associated parasitic resistance.
Solution Approach 2:
The contact structures are segmented into multiple sections along the vertical path, with intermediate contact points at different depths. This segmentation allows the current path to be divided into shorter segments, reducing the overall resistance and allowing more relaxed ground rules for each individual contact section while maintaining low total parasitic resistance.
Data Source
AI summary
Embodiments of staircase and contact structures of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device includes a semiconductor substrate and a plurality of through-substrate-trenches penetrating the semiconductor substrate. The 3D memory device also includes a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein the film stack includes alternating conductive and dielectric layers. The 3D memory device also includes a staircase structure formed at an edge of the film stack.