3D Memory Staircase Contact Layout for Dense Cell Stacking
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited due to the high cost of equipment required for miniaturization, necessitating the development of three-dimensional semiconductor memory devices with memory cells arranged in a stacked structure to increase density while reducing size.
Innovation Solution
A semiconductor memory device with a stacked structure featuring a first and second staircase portion, where contact plugs penetrate both structures, with the first contact plug electrically connected to the first stacked structure and not connected to the second, and the second contact plug connected to the second stacked structure and not connected to the first, allowing for reduced size and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional planar semiconductor devices are used, then manufacturing equipment cost is reduced, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked memory structures. Multiple memory cell layers are stacked vertically, with each layer containing memory cells formed between bit lines and word lines. This vertical stacking enables significantly higher integration density by utilizing the third dimension (height) rather than only expanding in the plane, thereby increasing the quantity of storage elements without proportionally increasing the footprint area.
Solution Approach 2:
The memory device is divided into multiple discrete stacked structures, each comprising separate memory cell layers. These stacked structures are arranged in an array with contact plugs positioned between them. The segmentation allows for modular fabrication and enables the integration density to be scaled by adding more stacked structures or increasing the number of layers within each stack, thus increasing the total quantity of memory cells.
2Quantity of substance
If three-dimensional stacked structures are implemented, then integration density is increased, but device complexity increases
Solution Approach 1:
Different contact plugs are assigned different electrical connection functions based on their local position. First contact plugs are configured to electrically connect to first stacked structures, while second contact plugs connect to second stacked structures. This local differentiation enables selective electrical access to specific memory layers through the bit line, simplifying the overall control architecture despite the increased physical complexity of the stacked structure.
Solution Approach 2:
The contact plugs serve multiple functions: they provide electrical connection between different stacked structures, serve as bit lines for data access, and enable selective addressing of memory cells in different layers. The stacked structures themselves function as both storage elements and as part of the addressing architecture, where the position of a contact plug determines which layers are accessed. This multi-functionality reduces the need for separate dedicated components.
Data Source
AI summary
A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.