3D Memory Staircase Structure for Uniform Insulating Layer Coverage
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Solution Overview
Problem
The increasing number of stacked layers in 3D NAND flash memory devices poses challenges in maintaining device performance and structural integrity due to issues with gap-filling capacity and side etching effects, particularly affecting the insulating layer coverage over conductive layers.
Innovation Solution
A three-dimensional memory device with a staircase structure is designed, where each stack unit has an inclined sidewall with gradually increasing slopes, allowing for improved coverage of the insulating layer and enhanced protection of conductive layers, achieved by forming a staircase shape with stack units that expose conductive-dielectric pairs at varying angles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the insulating layer is deposited to completely cover the conductive layer in conventional planar structures, then the coverage is complete, but the side etching effect damages the insulating layer and compromises structural integrity
Solution Approach 1:
The patent applies asymmetry by designing stack units with inclined sidewalls having different slopes on different sides, rather than symmetric vertical sidewalls. This asymmetric geometry allows the insulating layer to be deposited at angles that match the sidewall inclination, achieving complete coverage while preventing side etching damage to the insulating layer structure
Solution Approach 2:
The patent transitions from conventional two-dimensional planar structures to three-dimensional stacked structures with inclined sidewalls. By introducing the vertical dimension and varying slopes in the third dimension, the patent achieves complete insulating layer coverage while eliminating side etching effects that plague planar designs
2Quantity of substance
If the number of stacked layers is increased to achieve higher cell density, then storage capacity increases, but the side etching effect on the insulating layer worsens and device performance deteriorates
Solution Approach 1:
The patent employs nesting by stacking multiple layers of memory structures vertically, with each stack unit containing conductive layers and insulating layers nested within one another. The inclined sidewall design ensures that as layers are stacked, the insulating layer maintains complete coverage and structural integrity, enabling higher cell density without performance degradation
Solution Approach 2:
The patent changes the geometric parameters of the stack units by introducing inclined sidewalls with specific slope angles. This parameter modification allows the insulating layer to conformally cover the conductive layers even in multi-stack configurations, preventing side etching effects and maintaining device performance as cell density increases
3Ease of manufacture
If an insulating layer with poor gap-filling capacity is used, then the deposition process is simpler, but the layer coverage is incomplete and forms discontinuous or broken films
Solution Approach 1:
The asymmetric inclined sidewall geometry is specifically designed to work with insulating layers having poor gap-filling capacity. The slope angles are optimized so that during deposition, the insulating material can adequately cover the inclined surfaces without requiring complex gap-filling processes, achieving both manufacturing simplicity and complete coverage
Solution Approach 2:
The patent modifies the geometric parameters of the stack units (sidewall inclination angles) to accommodate insulating layers with limited gap-filling capability. By adjusting these parameters, the deposition process becomes simpler while still achieving complete and uniform coverage, eliminating the need for complex multi-step deposition procedures
Data Source
AI summary
The present disclosure provides a method of fabricating a three-dimensional memory device, and the three-dimensional memory device includes a substrate, and a memory stack structure. The memory stack structure is disposed on the substrate, and includes a plurality of stack units sequentially stacked into a staircase shape, wherein each of the stack units has a stepped slope, the stepped slope of any one of the stack units disposed in a related lower position is less than the stepped slope of another one of the stack units disposed over the one of the stack units. Through this arrangement, the three-dimensional memory device may therefore obtain an optimized structural integrity, as well as improved component efficiency.