3D Memory Staircase Structure With Offset Divisions for Higher Density
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, limiting memory density, which can be addressed by transitioning to a three-dimensional memory architecture.
Innovation Solution
The development of staircase structures in a three-dimensional memory device, where upper and lower staircase structures are formed with multiple layers and steps, allowing for increased density and complexity while maintaining manufacturing feasibility through specific etching and masking processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes using traditional fabrication techniques, then memory density is improved, but manufacturing complexity and costs increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional staircase structure (3D), enabling vertical stacking of memory layers. This dimensional change allows continued density improvement without further lateral scaling, avoiding the manufacturing complexity associated with sub-lithographic planar scaling
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but manufacturing costs increase
Solution Approach 1:
By stacking memory cells vertically in a three-dimensional staircase configuration, the patent achieves higher density using existing planar fabrication processes repeated across multiple layers, rather than requiring expensive new processes for further lateral scaling
3Quantity of substance
If three-dimensional memory architecture is implemented, then memory density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete layers and staircase segments, each formed by repeating standardized fabrication cycles. This segmentation allows precision requirements to be managed at each individual layer level rather than requiring ultra-precise single-step formation of the entire 3D structure
Solution Approach 2:
The patent forms complete alternating stacks of first and second dielectric layers and conductive layers as preliminary structures before creating the staircase patterns. This preliminary layer formation establishes a regular, repeatable foundation that simplifies subsequent patterning and reduces precision requirements during the staircase formation process
Data Source
AI summary
Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes an upper staircase structure and a lower staircase structure, wherein the upper staircase structure is formed in the first film stack and the lower staircase structure is formed in the second film stack. The upper and lower staircase structures are next to each other with an offset.