3D Semiconductor Memory Device With Staircase Dummy Structures
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Solution Overview
Problem
The integration density of two-dimensional (2D) semiconductor devices is limited due to the high cost of equipment needed for forming fine patterns, necessitating the development of three-dimensional (3D) semiconductor memory devices to increase memory cell density.
Innovation Solution
A method for manufacturing a 3D semiconductor memory device involving the formation of a substrate with a cell array region and connection regions, followed by the creation of a thin-layer structure with alternately stacked horizontal layers and insulating layers, and the use of etching processes to form dummy structures and electrode structures with staircase patterns at different levels, enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar semiconductor devices are used, then manufacturing equipment cost is reduced, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked in the vertical direction, with each layer containing memory cells formed by intersecting word lines and bit lines. This dimensional change dramatically increases integration density without requiring proportionally more expensive fine-patterning equipment, as the stacking approach leverages existing process capabilities in the vertical domain.
2Manufacturing precision
If fine pattern formation techniques are used to increase integration density, then memory cell density improves, but equipment cost increases significantly
Solution Approach 1:
The memory device is segmented into multiple discrete memory cell layers stacked vertically, with each layer containing a complete set of memory cells formed by word lines and bit lines. This segmentation allows the use of standard fine-patterning techniques for each individual layer rather than requiring ultra-fine patterning across the entire high-density structure, thereby reducing equipment cost while achieving high integration density through vertical stacking.
Solution Approach 2:
By moving the density increase strategy from the lateral plane to the vertical dimension, the patent avoids the need for extremely expensive ultra-fine lithography equipment. The vertical stacking of multiple memory cell layers achieves high integration density using conventional patterning processes repeated across layers, making manufacturing more economically feasible.
3Manufacturing precision
If three-dimensional vertically stacked structures are formed, then integration density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary formation of sacrificial structures, dummy structures, and template patterns before the actual memory cell formation. These preliminary structures guide the subsequent deposition and etching processes, ensuring precise alignment and positioning of word lines and bit lines in each vertical layer. This preliminary action simplifies the overall manufacturing process by providing a structured framework that directs material deposition and pattern transfer, reducing process complexity despite the three-dimensional architecture.
Solution Approach 2:
Dummy structures and sacrificial layers serve as intermediaries during the manufacturing process. These temporary structures facilitate the formation of complex three-dimensional patterns by providing masks, spacers, and alignment references during deposition and etching steps. After serving their guiding function, these intermediary structures are removed, having enabled the precise formation of the vertical memory stack without requiring direct complex patterning of the final structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach increases the integration density of semiconductor memory devices, overcoming the limitations of 2D devices by enabling more efficient use of space with vertically stacked electrodes and dummy structures, thereby improving performance and reducing manufacturing costs.
Implementation Method 1
forming a dummy structure by repeatedly performing a single-layer etching process on a portion of the thin-layer structure
Data Source
AI summary
A three-dimensional semiconductor memory device is provided. The memory device includes a substrate with a cell array region and a connection region adjacent to the cell array region, the connection region including a first pad region and a second pad region; an electrode structure including electrodes stacked on the substrate, the electrode structure including an upper portion forming an upper staircase structure; a first dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the first pad region; and a second dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the second pad region. Each of the first dummy structure and the second dummy structure includes a dummy staircase structure, and the first dummy structure is located at higher level than the second dummy structure.