3D Memory Staircase Elevation Against Conductor Dishing
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Solution Overview
Problem
In the fabrication of 3D memory devices, the dishing effect in the staircase region of dielectric stacks leads to conductor residual, which blocks the formation of word line contacts and results in memory function failure, as existing planarization methods like CMP cannot fully remove the conductor material.
Innovation Solution
An elevating dielectric layer is added to compensate for the dishing effect, allowing the source conductor layer to be fully planarized and preventing residual conductor material from blocking word line contact formation by ensuring the conductor layer can be completely removed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planarization methods like CMP are used to remove conductor material, then the conductor layer can be removed, but conductor residual remains due to dishing effect
Solution Approach 1:
An elevating dielectric layer is formed on the dielectric stack before depositing the source conductor layer. This preliminary action creates a compensating elevation that counteracts the dishing effect, allowing the subsequent planarization process to completely remove the conductor material without leaving residuals that would block word line contact formation.
Solution Approach 2:
The elevating dielectric layer acts as an intermediary between the dished dielectric stack and the source conductor layer. It provides a compensating elevation that enables complete conductor material removal while preventing the dishing effect from causing conductor residuals, thus mediating between the conflicting requirements of conductor removal and contact formation.
2Area of stationary object
If the source conductor layer is deposited to cover the dished region, then complete coverage is achieved, but conductor residual blocks word line contact formation
Solution Approach 1:
The elevating dielectric layer is formed in advance to create a compensating elevation in the dished region. This allows the source conductor layer to be deposited with complete coverage across the entire dielectric stack while the elevation prevents conductor residuals from forming in the previously dished areas, ensuring reliable memory function.
3Ease of manufacture
If the dishing effect is left uncorrected, then the fabrication process is simpler, but conductor residual causes memory function failure
Solution Approach 1:
Rather than attempting to correct dishing after conductor deposition, the elevating dielectric layer is formed preliminarily on the dielectric stack before conductor layer deposition. This approach maintains fabrication simplicity while effectively preventing conductor residuals and ensuring memory device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively eliminates conductor residual, enabling the successful formation of word line contacts and improving the functionality of 3D memory devices by increasing the planarization window and preventing memory cell blockages.
Implementation Method 1
the dishing effect in the staircase region of dielectric stacks leads to conductor residual
Implementation Method 2
allowing the source conductor layer to be fully planarized and preventing residual conductor material from blocking word line contact formation
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a first dielectric layer, and a second dielectric layer. The memory stack includes interleaved conductor layers and dielectric layers above the substrate. The memory stack includes a staircase structure at one edge of the memory stack. The channel structure extends vertically through the memory stack. The first dielectric layer is above the memory stack. A part of the first dielectric layer right above the staircase structure has a dished bottom surface. The second dielectric layer is on the part of the first dielectric layer right above the staircase structure and has a nominally flat top surface.