3D Memory Staircase Etch Control via Photoresist Trimming Rate Feedback
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Solution Overview
Problem
The challenge in 3D memory device fabrication is the difficulty in controlling the etch process for staircase structures due to the increase in thickness of the photoresist (PR) layer, which affects the precision and uniformity of the staircase formation, leading to challenges in achieving desired lengths and densities.
Innovation Solution
The method involves forming trimming marks on the dielectric stack and neighboring regions, measuring the actual PR trimming rate, comparing it to the estimated rate, and adjusting the PR trimming parameters to ensure precise control of the etching process, thereby maintaining uniformity and accuracy in staircase formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the photoresist layer thickness is increased to enable etching of thicker dielectric stacks for 3D memory structures, then the etching capability is improved, but the control precision and uniformity of the etching process deteriorates
Solution Approach 1:
The patent divides the single thick photoresist layer into multiple thinner layers, each etched separately to form individual staircases. This segmentation allows each thin layer to be precisely controlled during etching, avoiding the control issues associated with thick single-layer etching while achieving the required total etching depth for 3D memory structures.
Solution Approach 2:
The patent applies preliminary trimming to the photoresist layers before etching to pre-establish precise boundaries and dimensions. By performing this trimming action in advance, the subsequent etching process operates from a pre-controlled state, ensuring uniformity and precision in the final staircase structures even when dealing with multiple layers.
2Length of moving object
If multiple photoresist layers are used to achieve desired staircase lengths, then the etching depth capability is improved, but the process complexity increases
Solution Approach 1:
The patent employs a universal photoresist material and etching process that can be repeatedly applied to multiple layers. The same trimming and etching techniques used for the first layer are universally applied to subsequent layers, reducing the need for specialized procedures for each layer and managing process complexity through standardization.
Solution Approach 2:
The patent structures the fabrication process as nested sequential steps where each photoresist layer is formed, trimmed, and etched in a repeating pattern. Each layer's process is nested within the overall multi-layer fabrication sequence, allowing systematic control of staircase length accumulation while managing complexity through modular repetition of standardized sub-processes.
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.