3D Memory Staircase Etch Stop Structures for Precise Via Formation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming staircase etch stop structures, which are crucial for the integration of memory elements and electrical connectivity, leading to issues with memory array density and performance.
Innovation Solution
A method and structure involving an alternating stack of insulating and electrically conductive layers with staircase regions, where memory openings are filled with vertical stacks of memory elements, and discrete dielectric plates and contact via structures are formed to enable efficient electrical connectivity and memory element integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form staircase etch stop structures, then the manufacturing process is simpler, but the memory array density and performance are insufficient
Solution Approach 1:
The patent divides the continuous dielectric layer into discrete segmented dielectric layers, each forming a distinct etch stop structure at different heights. This segmentation enables precise control over etching depths at various regions, allowing complex three-dimensional memory architectures to be formed with high precision while managing structural complexity through modular layering
Solution Approach 2:
The patent introduces vertical dimensionality by forming dielectric layers at different heights and depths within the memory structure. The staircase etch stop structures create multiple vertical levels that enable complex three-dimensional memory arrays, transforming a two-dimensional planar structure into a multi-level three-dimensional architecture that increases storage density
2Manufacturing precision
If staircase etch stop structures are formed with high precision, then memory array density improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary formation of sacrificial layers and dielectric layers before final etching operations. By pre-positioning etch stop layers at specific heights and forming sacrificial structures in advance, the manufacturing process achieves high precision etch depths without requiring complex real-time control, simplifying the overall fabrication sequence
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures that facilitate the formation of staircase etch stop structures. These temporary sacrificial layers enable precise depth control during etching operations and are subsequently removed, acting as mediators that simplify the manufacturing process while achieving high precision results
3Quantity of substance
If memory elements are densely integrated, then storage capacity increases, but electrical connectivity formation becomes more difficult
Solution Approach 1:
The patent segments the memory structure into distinct functional layers (tunnel dielectric, charge trap dielectric, blocking dielectric, semiconductor layers) that can be independently formed and controlled. This segmentation allows memory elements to be densely integrated while maintaining clear separation between different electrical functions, simplifying the formation of electrical connectivity pathways through the stacked structure
Solution Approach 2:
The patent transitions from planar two-dimensional memory architecture to three-dimensional stacked architecture with memory elements arranged vertically. This dimensional change enables much higher memory element density while electrical connectivity is established through vertical vias and contact structures that connect different stacked layers, making connectivity formation more manageable despite increased density
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.