3D Memory Contact Structures Without Staircase Word-Line Routing
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Solution Overview
Problem
The scaling of planar memory cells in 3D NAND memory devices faces challenges due to process technology limitations and reliability issues, particularly as the staircase structure used for electrical contacts between word lines and control gates increases in size, reducing effective storage capacity and introducing mechanical stress.
Innovation Solution
A method for forming a three-dimensional memory structure that involves disposing an alternating dielectric stack on a substrate, forming contact openings by etching dielectric layer pairs, and creating a film stack of alternating conductive and dielectric layers to establish electrical connections without relying on a staircase structure, thereby reducing mechanical stress and enhancing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a staircase structure is used to provide electrical contacts between word lines and control gates, then electrical connections can be established, but the lateral dimensions of the staircase structure increase, reducing the effective storage capacity per area
Solution Approach 1:
The patent extracts and removes the staircase structure from the memory device, replacing it with direct vertical contact holes that penetrate through the dielectric layers to reach the control gates. This eliminates the lateral extension problem while maintaining electrical connectivity between word lines and control gates.
Solution Approach 2:
The patent transitions from a lateral/dimensional contact approach (staircase structure extending in the lateral direction) to a vertical contact approach (contact holes penetrating vertically through dielectric layers). This dimensional change allows electrical connections without consuming lateral storage area.
2Quantity of substance
If the number of vertically stacked memory cells is increased to increase storage capacity, then storage density improves, but the lateral dimensions of the staircase structure are also increased, reducing the effective storage capacity per area and introducing higher mechanical stress
Solution Approach 1:
The patent removes the staircase structure that causes mechanical stress concentration, replacing it with a simpler vertical contact hole architecture. This reduction in structural complexity decreases mechanical stress while allowing continued scaling of vertically stacked memory cells.
3Ease of manufacture
If the staircase structure is used to provide electrical contacts, then word lines can be connected to control gates, but the lateral dimensions increase which reduces effective storage capacity per area
Solution Approach 1:
The patent changes the contact formation approach from lateral staircase extension to vertical contact hole penetration. This dimensional shift maintains ease of manufacture through standard photolithography and etching processes while eliminating lateral dimension consumption.
Data Source
AI summary
Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.