3D Memory Peripheral Transistor Staircase Gate for High-Voltage Speed
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Solution Overview
Problem
The scaling down of transistor size in 3D memory devices to reduce planar areas occupied by peripheral circuits is hindered by increased cost and leakage current, and the requirement for high operational voltages above 5 volts, which complicates the reduction of peripheral circuit sizes following advanced CMOS technology nodes.
Innovation Solution
The implementation of transistors with a gate stack having a staircase structure, where the top surface above the channel area is higher than outside the channel area, enhances the control of the well region and improves the body effect, allowing for faster operation speeds and reduced voltage transmission loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to three-dimensional (3D) stacked memory architecture. Multiple memory strings are stacked vertically in the third dimension, allowing increased memory density without further scaling of individual cell dimensions. This dimensional change avoids the manufacturing complexities associated with continuing to scale planar features below the lithography limit.
2Quantity of substance
If feature sizes of memory cells approach lower limit, then memory density is improved, but fabrication process becomes challenging and costly
Solution Approach 1:
By stacking memory strings vertically in the third dimension, the patent achieves higher memory density without continuing to reduce feature sizes in the planar direction. This approach moves the fabrication challenge from extreme lateral scaling to more manageable vertical stacking, where standard lithography processes can be used.
3Speed
If more transistors are used in peripheral circuits, then operational speed is improved, but planar area increases
Solution Approach 1:
The patent places peripheral circuits in the third dimension above the memory array rather than expanding them laterally. This vertical arrangement allows additional transistors and circuit elements to be added without increasing the planar footprint, maintaining high operational speed while controlling area.
Solution Approach 2:
The patent embeds peripheral circuits within the 3D stacked structure, nesting control logic and driver circuits between or around memory strings. This nested arrangement allows multiple functional elements to occupy the same vertical space, increasing transistor count without proportionally increasing planar area.
Data Source
AI summary
A three-dimensional 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings, each of the memory strings extending through the memory stack. The peripheral device includes at least a transistor disposed on the substrate. The transistor includes a gate stack. The gate stack of the transistor includes a staircase structure, and an operational voltage of the transistor is above 5 volts.