3D Memory Staircase Structure for Dense and Reliable Gate Stacking
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and integration density while maintaining reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device design featuring a memory cell array region with a staircase structure, including alternately stacked interlayer insulating layers and gate layers, along with a separation structure, memory vertical structure, support vertical structure, and gate contact plugs, which are formed through specific manufacturing steps to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking by introducing multiple levels (first level, second level, third level) with gate layers, contact plugs, and insulating layers stacked vertically. This dimensional change enables increased storage capacity while maintaining a systematic manufacturing approach through repeated patterning and deposition processes at each level.
Solution Approach 2:
The memory device is segmented into distinct functional levels: first level with first gate layers and first contact plugs, second level with second gate layers and second contact plugs, and third level with third gate layers and third contact plugs. Each level can be manufactured using similar process steps, allowing modular fabrication that manages complexity through repetition of standardized units.
2Quantity of substance
If gate layers are stacked in vertical direction to increase integration density, then integration density increases, but structural stability and reliability may deteriorate
Solution Approach 1:
Interlayer insulating layers are introduced as intermediary structures between the stacked gate layers (first gate layers, second gate layers, third gate layers). These insulating layers electrically isolate adjacent gate layers while providing mechanical support and stress relief, preventing deformation and warpage that would otherwise compromise the structural integrity and reliability of the high-density vertical stack.
Solution Approach 2:
The vertical stack comprises a composite structure combining conductive gate layers with insulating interlayer insulating layers. This composite arrangement provides both the electrical functionality required for high integration density and the mechanical stability needed for reliability, as the contrasting material properties of conductors and insulators complement each other in the stacked configuration.
3Quantity of substance
If contact plugs are arranged at different levels to increase integration density, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
Contact plugs are segmented into distinct groups at different vertical levels: first contact plugs at the first level, second contact plugs at the second level, and third contact plugs at the third level. Each group can be aligned and formed using independent patterning and deposition processes, allowing manufacturing precision to be maintained for each level without requiring perfect simultaneous alignment of all levels, thereby enabling high integration density through staged fabrication.
Data Source
AI summary
A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.