3D Memory Array Layout Without Staircase Dummy Cells
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Solution Overview
Problem
Existing two-dimensional (2D) memory arrays face limitations in cell density within a given chip area, and there is a need for a more efficient three-dimensional (3D) memory array architecture that can enhance cell density and reduce chip area usage.
Innovation Solution
A 3D memory array architecture is developed with multiple 2D memory arrays stacked in a tableland feature, where sub-arrays are integrated without staircases between them, reducing the number of dummy memory cells and optimizing the layout to save chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D memory array architecture is used to increase cell density, then cell density is improved, but device complexity increases
Solution Approach 1:
The 3D memory array is divided into multiple 2D memory sub-arrays stacked vertically, with each sub-array containing memory cells arranged in a 2D grid. This segmentation allows the system to achieve high cell density through vertical stacking while maintaining the simplicity of 2D memory cell design in each layer, thus resolving the contradiction between increased cell density and architecture complexity.
Solution Approach 2:
The patent transitions from traditional 2D memory array layout to 3D stacked architecture by adding the vertical dimension (Z-axis). Multiple 2D memory sub-arrays are stacked one above another, connected via through-silicon vias (TSVs) and interconnect structures. This dimensional change enables significantly higher cell density without fundamentally changing the 2D memory cell design, thereby improving cell density while controlling architecture complexity.
2Reliability
If staircases are added between sub-arrays for proper connection, then electrical connectivity is improved, but chip area increases due to dummy memory cells
Solution Approach 1:
The patent extracts and removes the staircase structures from the 3D memory array design. Instead of using staircases to connect sub-arrays, the invention employs direct vertical interconnections through TSVs and interconnect layers. This extraction eliminates the need for dummy memory cells that would otherwise be required to fill the staircase voids, thereby reducing chip area while maintaining electrical connectivity through the removed staircase structures.
3Stability of the object's composition
If more dummy memory cells are included for staircase structures, then structural integrity is improved, but cell density decreases
Solution Approach 1:
The patent converts the harmful effect of staircase structures (which require dummy memory cells and reduce cell density) into a benefit by completely eliminating the staircases. The design uses direct vertical stacking of 2D memory sub-arrays connected through TSVs and interconnect layers, transforming the problematic staircase-induced area loss into a space-efficient vertical architecture that maximizes cell density while maintaining structural integrity through the interconnect system.
Data Source
AI summary
A 3D memory array includes a tableland feature formed with multiple 3D memory sub-arrays that are arranged in an X-axis direction. Each 3D memory sub-array includes multiple memory cells that are distributed in multiple columns arranged in the X-axis direction, multiple bit lines extending in a Z-axis direction, multiple source lines extending in the Z-axis direction, and multiple word lines extending in a Y-axis direction. Each memory cell includes a first electrode, a second electrode and a gate electrode. Each bit line interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction. Each bit line is electrically connected to another bit line of the same 3D memory sub-array, which is aligned with the bit line in the X-axis direction, and is electrically isolated from the bit lines of another 3D memory sub-array.