3D Memory Staircase Layout for Contact Overlay Margin
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Solution Overview
Problem
Three-dimensional memory devices face challenges in reducing contact coupling failures due to insufficient overlay margins during the formation of contacts, particularly in the hole forming process, which can lead to incomplete or faulty connections between electrode layers at different heights.
Innovation Solution
The solution involves configuring the staircase structures in the electrode stacks such that the pad regions of lower electrode stacks have a larger width than those of upper electrode stacks, thereby increasing the overlay margin and minimizing contact coupling failures by ensuring proper alignment and connection of contacts across varying heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are formed to connect electrode layers at different heights, then electrical signal application is enabled, but contact coupling failures occur due to insufficient overlay margins
Solution Approach 1:
The patent applies asymmetry by configuring staircase structures where pad regions of lower electrode stacks have larger widths than those of upper electrode stacks. This asymmetric width configuration creates larger overlay margins for lower contacts that require longer formation paths, thereby resolving the contradiction between contact connection reliability and manufacturing precision.
Solution Approach 2:
The patent introduces a dimensional variation in the width of pad regions across different vertical levels. By varying the width dimension of staircase structures at different heights, the patent provides additional adjustment capability to ensure proper contact alignment and connection, addressing the overlay margin issue through dimensional diversity.
2Ease of manufacture
If staircase structures with uniform width are used, then manufacturing is simplified, but contact coupling failures increase due to insufficient overlay margin
Solution Approach 1:
The patent applies local quality by making different parts of the staircase structures have different widths according to their specific functional requirements. Lower pad regions have larger widths to provide sufficient overlay margin for contacts formed at lower levels, while upper pad regions have smaller widths. This localized differentiation resolves the contradiction between ease of manufacture and contact coupling reliability.
3Reliability
If larger overlay margin is provided for lower contacts, then contact coupling reliability improves, but device area increases
Solution Approach 1:
The asymmetric width configuration of staircase structures provides larger overlay margins only where needed (at lower levels with longer contact formation paths), while maintaining smaller widths at upper levels. This selective application of larger dimensions resolves the contradiction between contact coupling reliability and device footprint by optimizing area usage according to actual requirements.
Data Source
AI summary
A three-dimensional memory device includes a plurality of electrode stacks stacked on a substrate in a vertical direction, each of the plurality of electrode stacks including a plurality of interlayer dielectric layers alternately stacked in the vertical direction with a plurality of electrode layers; and a plurality of staircase structures defined in the plurality of electrode stacks, each of the plurality of staircase structures configured by pad regions of electrode layers in an electrode stack that are disposed in a staircase shape, a staircase structure of an electrode stack lower in the plurality of electrode stacks has a larger width than a staircase structure of an electrode stack that is higher in the plurality of electrode stacks.