3D Memory Staircase Pad Layout for Top Word Line Resistance
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Solution Overview
Problem
In 3D memory devices, the topmost conductive layer between the staircase region and the array region experiences high resistance due to damage from the contact landing pad process, leading to gate control failures.
Innovation Solution
A memory device design that includes a thicker protective layer to prevent consumption of the underlying sacrificial layer, maintaining the topmost conductive layer's thickness and reducing resistance, thereby improving gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact landing pad process is performed to form pads and contacts, then interconnection structures are created to connect components, but the topmost oxide layer is etched forming a recess that damages the underlying sacrificial layer, resulting in high resistance or open issues in the topmost word line
Solution Approach 1:
A thicker protective layer is formed before the contact landing pad process to prevent consumption of the underlying sacrificial layer. This preliminary protective measure ensures that when etching occurs during pad formation, the sacrificial layer remains intact, allowing the topmost conductive layer to maintain sufficient thickness after gate replacement, thereby reducing resistance and improving gate control reliability
Solution Approach 2:
The thicker protective layer acts as a cushioning layer that absorbs the damage from the etching process during contact landing pad formation. By providing this additional protective buffer beforehand, the underlying sacrificial layer is protected from being consumed, ensuring the topmost conductive layer maintains its thickness and electrical performance
Data Source
AI summary
Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.