3D Memory Word-Line Routing With Dual Staircase Drivers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing two-dimensional non-volatile memory designs limit storage capacity, and as three-dimensional memory storage capacity grows, the interconnection between three-dimensional memory and driving devices becomes increasingly complex, requiring innovative solutions to manage routing and reduce the number of metallization layers.
Innovation Solution
The implementation of a three-dimensional memory device with staircase structures at opposite sides, where word lines are routed to separate word line driving circuits on each side, allowing for independent routing and sharing of metallization layers, reducing the complexity and cost of interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory stacking is implemented to increase storage capacity, then storage capacity is improved, but interconnection complexity increases
Solution Approach 1:
The memory device is divided into two separate stacking structures, each with its own word line driving circuit. This segmentation allows independent routing of word lines to different sides of the bit line, reducing the complexity of interconnections by distributing the routing load across multiple independent paths rather than requiring all word lines to route through a single complex interconnection system.
Solution Approach 2:
The patent utilizes three-dimensional stacking architecture where memory cells are arranged in multiple vertical layers. By extending the memory structure in the vertical dimension rather than only in the planar area, the device achieves increased storage capacity while managing interconnection complexity through the spatial separation provided by the stacked configuration.
2Adaptability or versatility
If more metallization layers are added to route word lines to all memory cells, then interconnection completeness is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The word line routing is segmented into two separate groups, with each group routed to a different side of the bit line through dedicated word line driving circuits. This segmentation allows each metallization layer to have a simpler, more focused routing pattern rather than requiring complex global interconnections, thereby reducing manufacturing complexity while maintaining complete interconnection coverage.
Solution Approach 2:
The patent combines the routing of word lines to opposite sides of the bit line through a shared stacking structure. By merging the routing paths at the top and bottom of the stacked memory cells, the design achieves complete interconnection without requiring separate metallization layers for each side, thus reducing the total number of metallization layers needed.
Data Source
AI summary
An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.