3D Memory Staircase Contacts With Support Structures for Higher Layer Counts
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Solution Overview
Problem
The challenge in 3D memory device manufacturing lies in controlling the word line replacement process as the number of layers increases, leading to difficulties in supporting the dielectric stack and maintaining contact structure landing windows, which restricts the size reduction and layer count of 3D semiconductive devices.
Innovation Solution
The implementation of a 3D memory device structure featuring a stack with alternating conductive and dielectric layers, including staircase structures and support structures that align with contact structures, enhances manufacturing strength and expands the contact landing window, allowing for increased layer counts and device size without conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in 3D memory device is increased to improve memory density, then the memory capacity is improved, but the manufacturing difficulty and complexity increase
Solution Approach 1:
The device is segmented into multiple functional components: staircase structure for contact alignment, support structures for mechanical reinforcement, and alternating conductive/dielectric layers. This segmentation allows each component to address specific manufacturing challenges independently, enabling higher layer counts without proportionally increasing overall manufacturing complexity.
Solution Approach 2:
Support structures are formed in advance during the manufacturing process to provide preliminary mechanical reinforcement to the dielectric stack. This preliminary action prevents structural collapse during subsequent processing steps, enabling the fabrication of higher-layer devices that would otherwise be too fragile to manufacture.
2Quantity of substance
If the layer count is increased to improve memory density, then the storage capacity is improved, but the structural stability of dielectric stack deteriorates
Solution Approach 1:
Support structures are formed within the dielectric stack during the manufacturing process to provide preliminary mechanical reinforcement. These support structures prevent stack collapse and maintain structural integrity throughout subsequent processing steps, enabling stable fabrication of high-layer-count devices.
Solution Approach 2:
The dielectric stack is constructed as a composite structure with alternating conductive and dielectric layers, reinforced with support structures. This composite architecture provides both electrical functionality and mechanical stability, allowing the stack to maintain its composition stability even as layer count increases.
3Area of moving object
If the contact structure landing window is reduced to improve device miniaturization, then the device size is reduced, but the manufacturing precision requirement increases
Solution Approach 1:
The staircase structure acts as an intermediary element between the contact structures and the underlying memory layers. It provides multiple alignment references and a gradual transition zone that compensates for manufacturing variations, allowing contact structures to be accurately positioned without requiring extremely high precision in a single step.
Solution Approach 2:
The contact structure formation process is segmented into multiple steps with the staircase structure providing intermediate alignment levels. This segmentation breaks down the high-precision requirement into multiple lower-precision steps, making the overall process more manufacturable while achieving the same final alignment accuracy.
4Length of moving object
If the feature size is reduced to improve planar memory scaling, then the memory cell size is reduced, but the process technology becomes challenging and costly
Solution Approach 1:
The invention transitions from planar 2D scaling to 3D vertical stacking architecture. Instead of continuously reducing feature sizes in the planar direction, memory capacity is increased by stacking multiple layers vertically. This dimensionality change avoids the diminishing returns and escalating costs associated with sub-10nm planar scaling while maintaining manufacturing feasibility.
Data Source
AI summary
A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes conductive layers and dielectric layers stacked alternatingly, and the stack includes a staircase structure. Each contact structure extends through the insulating structure and is in contact with a respective conductive layer in the staircase structure. The support structures extend through the stack in the staircase structure. The contact structures are arranged in a first row and a second row, the first row of contact structures is in electrical contact with the peripheral device, and the second row of contact structures is in electrical insulation with the peripheral device.