3D Memory Staircase Layout for Higher Etch-Trim Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing multi-cycle etch and trim processes for forming staircase structures in 3D memory devices suffer from low throughput and high costs, making it challenging to efficiently connect a large number of word lines to semiconductor channels in 3D memory devices.
Innovation Solution
The proposed solution involves forming a 3D memory device with multiple staircase structures on both sides of the channel structure region, each comprising division block structures with staircases arranged in different directions, using a specific etch-trim process to reduce the number of masks and trimming processes, thereby increasing etching efficiency and reducing the thickness of mask layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing multi-cycle etch and trim processes are used to form staircase structures, then word lines can be connected to semiconductor channels, but the throughput is low and costs are high
Solution Approach 1:
The staircase structure is divided into multiple division blocks, where each division block contains a subset of steps. This segmentation allows different division blocks to be formed in parallel using separate masks, reducing the total number of sequential trimming processes and increasing throughput while maintaining the required connectivity between word lines and semiconductor channels.
2Quantity of substance
If more oxide/nitride layers are added to 3D memory devices, then memory density increases, but the existing multi-cycle etch and trim processes become less efficient
Solution Approach 1:
The patent introduces a lateral dimension to the formation process by dividing the staircase structure into multiple division blocks that can be formed simultaneously in different lateral positions. This dimensional approach allows the etching process to handle increased numbers of oxide/nitride layers more efficiently by processing multiple regions in parallel rather than sequentially through multiple trimming cycles.
Data Source
AI summary
A three-dimensional (3D) memory device includes a plurality of channel structures extending along a vertical direction, a first staircase structure including a plurality of division block structures arranged along a first direction on a side of the channel structures, and a top select gate staircase structure disposed between the channel structures and the first staircase structure in a second direction that is different from the first direction. At least one of the division block structures includes a plurality of staircases arranged along the second direction. At least one of the staircases includes a plurality of steps arranged along the first direction.