3D Memory Staircase Structure for Reliable Word Line VIA Contacts
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Solution Overview
Problem
The challenge in 3D memory devices is forming word line VIA contacts on staircase structures without causing short circuits or punch-through, as conventional etching processes lead to over-etching and interference between conductor layers at different stairs, making it difficult to achieve high storage capacity without increasing fabrication complexity.
Innovation Solution
The implementation of a staircase structure with a conductor portion on top of each stair and a dielectric structure underneath, where the conductor portion covers the landing area and has a varying width along the lateral direction, reducing interference and enabling precise formation of word line VIA contacts, and using an ion implantation process to alter the etch rate of sacrificial layers for efficient formation of lateral recesses and conductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form word line VIA contacts on staircase structures, then the fabrication process is simple, but over-etching occurs causing interference between conductor layers at different stairs and leading to short circuits
Solution Approach 1:
The patent applies preliminary action by forming a protective sacrificial layer (e.g., silicon nitride) over the conductor portions before the etching process. This sacrificial layer is deposited in advance to protect the conductor layers from over-etching during the formation of word line VIA contacts. The protective layer is removed selectively after the etching is complete, preventing short circuits between conductor layers at different stairs while maintaining fabrication feasibility.
Solution Approach 2:
The patent uses a sacrificial protective layer as an intermediary element between the etching process and the conductor layers. This intermediary layer mediates the etching process by being resistant to the etchant, thereby protecting the conductor portions from damage. The sacrificial layer is selectively removed after serving its protective function, enabling precise formation of word line VIA contacts without causing interference between conductor layers.
2Reliability
If the conductor portion width is uniform along the lateral direction, then the fabrication process is simpler, but interference between adjacent stairs occurs leading to punch-through
Solution Approach 1:
The patent applies local quality by making the conductor portion width variable along the lateral direction rather than uniform. Specifically, the conductor portion has a first width at one end and a second width at the other end, with the second width being smaller than the first width. This gradual narrowing reduces interference between adjacent stairs and prevents punch-through, while the varying width is achieved through standard photolithography and etching processes, maintaining fabrication simplicity.
3Reliability
If the staircase structure divides the memory array into separate sections, then interference between conductor layers is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the memory array structure into multiple sections using the staircase structure. The staircase structure includes multiple stairs with conductor portions and dielectric portions that segment the memory array along the lateral direction. This segmentation physically separates conductor layers at different stairs, reducing interference between them. The segmented structure is integrated into the existing 3D NAND architecture, achieving interference reduction while maintaining overall device compactness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents punch-through and short circuits, allows for the formation of reliable word line VIA contacts, and enhances the fabrication process by reducing leakage and complexity, thereby improving the storage capacity of 3D memory devices.
Implementation Method 1
using an ion implantation process to alter the etch rate of sacrificial layers for efficient formation of lateral recesses and conductor layers
Data Source
AI summary
In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.