3D Memory Staircase Via Layout for Higher Word-Line Integration
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Solution Overview
Problem
The challenge in three-dimensional memory devices is to increase the degree of integration while managing the increased number of word lines, which leads to a higher number of wiring lines, resulting in a decrease in integration due to the need for more coupling wiring lines and limited space for vertical vias.
Innovation Solution
The solution involves a three-dimensional memory device structure with stacked word lines and interlayer dielectric layers, where the upper and lower stacks have overlapping staircase and coupling parts, allowing vertical vias to pass through without requiring separate openings, thereby increasing the number of vertical vias and preventing alignment failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to increase the degree of integration, then the storage capacity is improved, but the number of wiring lines needed to couple the word lines and row decoder increases, resulting in a decrease in the degree of integration
Solution Approach 1:
The patent transitions from a planar wiring layout to a three-dimensional stacked architecture. Word lines are arranged in multiple vertical stacks (first stack, second stack, third stack) at different heights, allowing wiring lines to be routed through vertical vias connecting different stacking levels. This dimensional transition enables more word lines to be coupled without proportionally increasing the planar wiring area, thus resolving the contradiction between increasing word line quantity and maintaining integration density.
Solution Approach 2:
The patent implements a nested structure where multiple word line stacks are vertically arranged and interconnected through shared vias. The first, second, and third stacks are positioned at different heights and connected through overlapping via structures, creating a compact nested arrangement. This nesting allows multiple word lines to share common wiring paths and coupling points, reducing the total number of discrete wiring lines needed while maintaining high word line count.
2Quantity of substance
If the number of vertical vias is increased to accommodate more word lines, then the degree of integration is improved, but the available space for via formation is limited
Solution Approach 1:
The patent utilizes vertical stacking to distribute vias across multiple height levels. Instead of concentrating all vias in a single planar layer, the first, second, and third stacks are arranged at different vertical positions with overlapping via regions. This allows the device to accommodate more total vias without increasing the planar footprint, as vias are distributed throughout the vertical dimension.
Solution Approach 2:
The patent merges via structures across multiple stacks by positioning the first, second, and third stacks such that their via regions overlap vertically. Common vias serve multiple word line stacks simultaneously, reducing the total number of discrete via openings needed. For example, a via in the first stack may also serve as a via for the second or third stack, consolidating wiring paths and saving planar space.
Data Source
AI summary
A method for manufacturing a three-dimensional memory device comprises: forming a first pre-stack by alternately stacking a plurality of first interlayer dielectric layers and a plurality of first sacrificial layers in a vertical direction; forming, in the first pre-stack, a first staircase part; forming a plurality of first vertical vias, which pass through the first staircase part, and a plurality of second vertical vias that pass through a first coupling part of the first pre-stack; forming a second pre-stack by alternately stacking a plurality of second interlayer dielectric layers and a plurality of second sacrificial layers on the first pre-stack; forming, in the second pre-stack, a second staircase part; forming a plurality of third vertical vias and a plurality of fourth vertical vias; and replacing the first and second sacrificial layers with an electrode material.