3D Memory Staircase Structure for Higher Throughput Word-Line Access
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Solution Overview
Problem
Planar memory cells face density limitations and high fabrication costs as feature sizes approach a lower limit, and existing multi-cycle trim and etch processes for 3D memory devices suffer from low throughput and high expense.
Innovation Solution
A method for forming a staircase structure in 3D memory devices involving an alternating layer stack, patterning a mask stack to define staircase regions, and forming multiple-step staircase structures through repetitive etch-trim processes to connect word lines, reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing multi-cycle trim and etch processes are used to form staircase structures, then electrical connections for word lines are achieved, but fabrication complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple trim and etch cycles into a single integrated process. The method forms staircase structures by performing one trim operation followed by one etch operation, rather than requiring separate multi-cycle processes. This merging reduces fabrication complexity while maintaining the necessary electrical connections for word lines in 3D memory devices.
Solution Approach 2:
The patent creates a universal staircase formation process that can be applied across different regions of the 3D memory device. By forming multiple staircase structures using the same trim-etch sequence, the process achieves multi-functionality, reducing the need for region-specific fabrication steps and thereby lowering overall manufacturing complexity.
2Reliability
If existing multi-cycle trim and etch processes are used to form staircase structures, then electrical connections for word lines are achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple trim and etch cycles into a single integrated process. The method forms staircase structures by performing one trim operation followed by one etch operation, rather than requiring separate multi-cycle processes. This merging reduces fabrication complexity while maintaining the necessary electrical connections for word lines in 3D memory devices.
Solution Approach 2:
The patent employs a disposable mask layer that is formed, patterned, and then removed after serving its purpose in defining the staircase structure. This approach eliminates the need for complex mask reuse and regeneration processes, reducing manufacturing cost while maintaining electrical connection reliability.
3Quantity of substance
If planar memory cell feature sizes are reduced to increase density, then storage capacity increases, but fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar memory cell architecture to three-dimensional stacked architecture. By stacking multiple memory layers vertically, the device achieves higher storage density without requiring further reduction of planar feature sizes. This dimensional transition maintains fabrication feasibility while significantly increasing the quantity of storage cells.
4Quantity of substance
If more oxide/nitride layers are stacked to increase memory density, then storage capacity increases, but staircase formation throughput decreases
Solution Approach 1:
The patent combines multiple trim and etch cycles into a single integrated process. The method forms staircase structures by performing one trim operation followed by one etch operation, rather than requiring separate multi-cycle processes. This merging reduces fabrication complexity while maintaining the necessary electrical connections for word lines in 3D memory devices.
Solution Approach 2:
The patent implements a continuous staircase formation process where the trim and etch operations are performed in sequence without intermediate masking or re-alignment steps. This continuous action increases throughput by eliminating process interruptions, allowing efficient formation of staircase structures even as the number of oxide/nitride layers increases to boost memory density.
Data Source
AI summary
A memory device includes a stack including conductive layers and insulating layers alternatingly stacked in a first direction, a semiconductor channel extending through the stack in the first direction, and a staircase structure including sub-staircase structures in a second direction perpendicular to the first direction. One of the sub-staircase structures includes two portions arranged along the second direction. Each of the portions includes first staircases arranged in the second direction and second staircases arranged in a third direction perpendicular to the first direction and the second direction.