3D Memory Lateral Block Isolation for Stairless Word Line Contacts

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Solution Overview

Problem

Current three-dimensional memory devices face challenges in efficiently forming inter-block word line lateral isolation structures for stairless layer contact via structures, which affects the performance and reliability of memory arrays.

Innovation Solution

The solution involves forming an alternating stack of insulating and sacrificial material layers over a substrate, creating memory openings and support openings, and replacing sacrificial material layers with electrically conductive strips, while using dielectric isolation structures and backside trenches to achieve lateral isolation and electrical isolation between memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional three-dimensional memory devices are used, then manufacturing processes are simpler, but electrical isolation between memory blocks is insufficient and performance is degraded

Engineering Contradiction:
Improveelectrical isolation between memory blocksVSAvoidisolation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure is segmented into multiple functional components: dielectric isolation structures that vertically extend through alternating stacks, backside trenches that laterally extend between memory blocks, and trench fill structures that fill the trenches. This segmentation allows each component to perform its specific isolation function independently, achieving comprehensive electrical isolation while maintaining manageable manufacturing complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces lateral isolation through backside trenches that extend in the horizontal direction, complementing the vertical isolation provided by dielectric isolation structures. This multi-dimensional approach to isolation ensures complete electrical separation between memory blocks in both vertical and lateral directions, significantly improving reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If stairless layer contact via structures are formed, then device performance is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecontact via formation reliabilityVSAvoidvia alignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Backside trenches are formed in advance before contact via formation, creating pre-defined isolation boundaries and structural guides. This preliminary action establishes a robust framework that simplifies subsequent via formation processes and reduces alignment precision requirements by providing physical reference structures

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Trench fill structures serve as intermediary elements that fill the backside trenches and provide mechanical support and electrical isolation during the contact via formation process. These intermediary structures act as sacrificial or permanent elements that facilitate precise via formation while maintaining the stairless layer architecture

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240194263A1Three-dimensional memory devices with lateral block isolation structures and methods of forming the same
Publication Date: 2024.06.13 SANDISK TECHNOLOGIES LLC
  • US20240194263A1 patent drawing
  • US20240194263A1 patent drawing
  • US20240194263A1 patent drawing

AI summary

A memory device includes an alternating stack of insulating layers and composite layers that alternate along a vertical direction, where each of the composite layers includes a combination of a dielectric connection plate and a plurality of electrically conductive strips that are laterally spaced apart by backside trench isolation structures, arrays of memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and dielectric isolation structures adjoined to an end portion of a respective one of the backside trench fill structures.