3D Memory Word Line Via Structure With Stepped Backside Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in forming efficient backside word line contact via structures in three-dimensional semiconductor devices, particularly in creating stepped surfaces and replacing sacrificial materials with conductive layers to achieve optimal contact with word lines.
Innovation Solution
The method involves forming an alternating stack of insulating and sacrificial material layers, patterning to create memory and contact via openings, replacing sacrificial materials with conductive layers, and forming stepped surfaces to ensure efficient contact via structures that decrease in lateral extent vertically, allowing for effective contact with top surfaces of electrically conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sacrificial material layers are replaced with electrically conductive layers to form word line contacts, then electrical connectivity is improved, but the manufacturing process complexity increases due to multiple patterning and material replacement steps
Solution Approach 1:
The patent applies preliminary action by forming the alternating stack of insulating and sacrificial material layers before the final conductive layers are deposited. The sacrificial structures are prepared in advance with specific patterns and positions, allowing subsequent conductive layers to be directly formed in the correct locations without requiring complex in-situ patterning during the conductive layer formation process.
Solution Approach 2:
The sacrificial material layers serve as intermediary structures that facilitate the formation of the final conductive word line contacts. These temporary sacrificial structures are used during manufacturing to define the positions and shapes of the conductive contacts, then are replaced with the actual conductive materials. This intermediary approach simplifies the overall process compared to directly forming the complex conductive contact patterns in a single step.
2Productivity
If stepped surfaces are formed by patterning the alternating stack with decreasing lateral extents, then contact via structure efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the contact via structure formation into discrete stepped levels, where each level corresponds to a specific word line contact height. The alternating stack is patterned with insulating and sacrificial layers that create these segmented steps, allowing each contact via to be formed at the appropriate height for its corresponding word line. This segmentation approach improves efficiency by enabling parallel formation of multiple contact vias at different heights without requiring complex continuous patterning.
3Reliability
If the topmost surface of the layer contact via structure is positioned below the horizontal plane of the alternating stack, then short circuit prevention is improved, but the contact via structure depth increases
Solution Approach 1:
The patent applies local quality by creating variations in the depth and positioning of different contact via structures across the device. Not all contact vias are formed to the same depth or positioned at the same vertical level. Instead, each contact via is locally optimized based on its specific requirements - some extend deeper to reach lower word lines, while others are shallower for upper word lines. This local differentiation prevents short circuits between adjacent contacts while maintaining appropriate electrical connectivity for each word line.
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer, contacting a top surface of a topmost electrically conductive layer within the subset of the electrically conductive layers, and having a topmost surface below a horizontal plane including a topmost surface of the alternating stack.