3D Semiconductor Memory Cell Structure With Stepped Contacts
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by physical constraints, necessitating a new approach to increase capacity.
Innovation Solution
A 3D semiconductor memory device with stacked memory cells and a unique contact electrode structure, including a first and second step structure with varying thicknesses, connected by a monocrystalline channel layer and insulated by an interlayer insulating layer, allowing for increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If 2D semiconductor memory device structure is used, then manufacturing process is simple, but integration density is limited by physical constraints
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by introducing vertical stacking of memory cells. Multiple memory cells are stacked in the vertical direction (third direction perpendicular to substrate) to form a 3D architecture, thereby increasing integration density without being constrained by the physical limitations of 2D scaling.
2Reliability
If contact electrodes have uniform thickness, then manufacturing is simple, but connection reliability between stacked cells is insufficient
Solution Approach 1:
The contact electrodes are designed with non-uniform thickness where different portions have different thicknesses. Specifically, the first contact electrode has a first thickness in the vertical direction, while the second contact electrode has a second thickness greater than the first thickness. This local variation in thickness provides enhanced connection reliability at critical interfaces while maintaining manufacturing feasibility.
3Manufacturing precision
If memory cells are stacked vertically to increase integration density, then capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The stacked memory cell structure is divided into multiple distinct layers with clear interfaces. Each memory cell layer includes separated components such as transistor bodies, capacitor structures, and contact electrodes with defined thicknesses. This segmentation into discrete, manufacturable units facilitates precise stacking while maintaining high integration density.
4Reliability
If interlayer insulating layer is introduced between stacked contact electrodes, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
An interlayer insulating layer is introduced as an intermediary between the first contact electrode and the second contact electrode in the vertical stacking direction. This insulating layer provides necessary electrical isolation between adjacent contact electrodes while enabling the overall 3D stacked architecture to function reliably.
Data Source
AI summary
A semiconductor memory device includes a substrate, contact electrodes extending in a first direction, each of the contact electrodes including a connection portion having a first thickness and a landing portion having a second thickness, an uppermost contact electrode above the contact electrodes, the contact electrodes being longer in the first direction than the uppermost contact electrode and defining a step structure, transistor bodies extending in a second direction and having a first source/drain, a monocrystalline channel layer, and a second source/drain sequentially arranged in the second direction, the monocrystalline channel layer being connected to a corresponding contact electrode, a lower electrode layer connected to the second source/drain of each of the transistor bodies, a capacitor dielectric layer covering the lower electrode layer and having a uniform thickness, and an upper electrode layer separated from the lower electrode layer by the capacitor dielectric layer.