3D Memory Cell Structure With Stepped Gate Pads for Uniform Patterning
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and improving integration and mass-productivity, particularly in the design and manufacturing processes of three-dimensionally arranged memory cells.
Innovation Solution
The semiconductor device incorporates a source structure with distinct regions, gate electrodes forming a step structure, separation patterns, and vertical structures with a common lattice arrangement, which simplifies the manufacturing process and enhances integration and productivity by allowing for continuous and uniform patterning and reducing process dispersion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are implemented to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The substrate is divided into a first region and a second region, with different structure configurations in each region. The gate electrodes are segmented into pad regions and non-pad regions, allowing different structural approaches in different areas to manage complexity while maintaining high storage capacity
Solution Approach 2:
The patent transitions from two-dimensional to three-dimensional memory cell arrangement by stacking gate electrodes and creating vertical structures. Multiple gate electrodes are arranged in the vertical dimension, significantly increasing storage capacity per unit area while using systematic patterning methods to control the resulting complexity
2Manufacturing precision
If continuous and uniform patterning is implemented, then manufacturing precision is improved, but ease of manufacture may be affected by process constraints
Solution Approach 1:
The gate electrodes are designed with pad regions that extend beyond the channel region in advance, creating a stepped structure. This preliminary extension simplifies subsequent manufacturing steps by providing built-in alignment features and reducing the need for complex additional patterning operations
Solution Approach 2:
The patent creates a stepped structure where pad regions of gate electrodes are at a higher level than non-pad regions, establishing equipotential zones that simplify electrical connection and alignment during manufacturing. This uniform stepped design across the substrate makes the manufacturing process more predictable and easier to control
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: a first structure including a substrate, circuit elements on the substrate, and lower interconnections on the circuit elements; and a second structure on the first structure, the second structure including: a source structure having a first region and a second region; gate electrodes provided on the source structure and spaced apart from each other, extending in a first direction parallel to an upper surface of the substrate, and including pad regions forming a step structure on the second region; separation patterns passing through the gate electrodes and extending in the first direction; first vertical structures provided between the separation patterns on the first region and extending through the gate electrodes; and second vertical structures provided between the separation patterns, on the second region and extending through the pad regions of the gate electrodes, the second vertical structures and the first vertical structures having a common lattice arrangement