3D Memory Stack Stepped Groove Layout for Simpler Etching
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the high cost of equipment required for miniaturizing fine patterns, and existing three-dimensional devices face challenges in manufacturing complexity and yield due to the need for multiple etching processes and mask formations.
Innovation Solution
A semiconductor memory device with a structure featuring alternately stacked conductive layers and interlayer insulating layers, including stepped grooves and an opening with multiple steps on its sidewalls, which allows for the reduction of manufacturing steps and improves structural stability, thereby reducing manufacturing time and cost while enhancing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etching processes and mask formations are used to create complex three-dimensional structures, then manufacturing precision can be improved, but device complexity and manufacturing time increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-forming sacrificial layers (such as silicon oxide or silicon nitride) between the conductive layers before the final etching process. These sacrificial layers create predetermined patterns that guide subsequent etching, eliminating the need for multiple separate mask formations and etching steps. The sacrificial layers are removed after defining the desired three-dimensional structure, achieving complex geometries through a simplified process sequence.
Solution Approach 2:
The patent uses sacrificial layers as intermediary materials that facilitate the formation of complex three-dimensional structures. These intermediary layers (silicon oxide, silicon nitride) are deposited between conductive layers and serve as temporary structural elements during manufacturing. They mediate the transformation from planar to three-dimensional structures by providing physical support and pattern definition during the etching process, then are removed to complete the final structure.
2Stability of the object's composition
If more manufacturing steps are implemented to achieve complex three-dimensional structures, then structural stability can be improved, but productivity decreases due to increased manufacturing time
Solution Approach 1:
The patent merges multiple manufacturing operations into a single integrated process. Instead of performing separate mask formation, etching, and structural support steps, the method combines these operations by using sacrificial layers that simultaneously provide pattern definition, structural support during etching, and eventual removal to create the final three-dimensional structure. This merging reduces the total number of process steps while maintaining structural integrity.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining the sacrificial layers throughout the etching process. These layers continuously provide structural support and pattern definition from the initial etching step through to the completion of the three-dimensional structure formation. The continuous presence of these intermediary elements ensures structural stability throughout the manufacturing process without requiring intermittent reinforcement steps.
3Ease of manufacture
If conventional two-dimensional memory structures are used, then manufacturing cost can be kept low, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional memory structures by vertically stacking conductive layers (word lines, bit lines, select lines) and channel structures. This dimensional change increases integration density by utilizing the vertical space above the substrate rather than only the planar area. The three-dimensional arrangement allows multiple memory cells to be stacked vertically, significantly increasing the quantity of storage elements per unit area while using manufacturing processes that remain relatively cost-effective.
Data Source
AI summary
A semiconductor memory device includes a first stack including a plurality of conductive layers and a plurality of first interlayer insulating layers alternately stacked on a substrate; a second stack including a plurality of sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the substrate; a plurality of stepped grooves defined at different depths in the first stack; and an opening defined in the second stack, and having, on a sidewall thereof, a plurality of steps which have the same heights as differences in depth between the plurality of stepped grooves.