3D Memory Contact Vias Across Multi-Level Stepped Layers
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in effectively forming contact via structures on multi-level stepped surfaces, which hinders the efficient integration of memory stack structures and affects the overall performance and reliability of the devices.
Innovation Solution
The solution involves forming an alternating stack of insulating and electrically conductive layers with a terrace region having steps, a retro-stepped dielectric material portion, and laterally isolated contact structures with specific via structures and spacers, allowing for precise contact formation between conductive layers across stepped surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional contact via structures are used on multi-level stepped surfaces, then device complexity is reduced, but manufacturing precision deteriorates due to difficulty in forming reliable contacts across varying elevation levels
Solution Approach 1:
The patent introduces a vertical dimension solution by forming via structures that extend through multiple elevation levels of the stepped surface. Instead of attempting to form contacts purely in the lateral plane, the via structures utilize the vertical dimension to penetrate through the stepped terrain, enabling reliable electrical connections between conductive layers at different heights while maintaining manufacturing precision.
Solution Approach 2:
The patent employs dielectric materials as intermediary substances that fill and surround the via structures. These dielectric materials provide mechanical support, electrical insulation, and stress distribution, enabling the via structures to maintain their shape and functionality across the multi-level stepped surface without requiring complex support structures.
2Reliability
If laterally isolated contact structures with spacers are implemented, then contact reliability improves, but device complexity increases due to additional structural components
Solution Approach 1:
The patent divides the contact structure into functionally distinct segments: the via structure itself, the dielectric spacer material surrounding it, and the conductive fill material within it. This segmentation allows each component to be optimized independently - the via provides the electrical pathway, the dielectric spacer provides isolation and structural support, and the conductive material ensures low-resistance contact - thereby improving overall contact reliability while managing complexity through functional decomposition.
Solution Approach 2:
The patent applies different material properties to different regions of the contact structure. The via regions are filled with conductive materials for electrical connectivity, while the surrounding regions are filled with dielectric materials for insulation and mechanical support. This local differentiation of material qualities enables reliable electrical contacts while using simple, standard semiconductor materials and processes.
3Ease of manufacture
If via structures extend through multiple conductive layers at different steps, then integration of memory stack structures improves, but manufacturing difficulty increases
Solution Approach 1:
The patent designs the via structure formation process to be universal across multiple conductive layers and stepped regions. The same via formation methodology - involving dielectric filling, spacer deposition, and conductive material insertion - is applied consistently regardless of the specific elevation level or conductive layer being accessed. This universal approach simplifies manufacturing by eliminating the need for different processes for different locations, thereby improving ease of manufacture despite the complex multi-level geometry.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing a terrace region having a plurality of steps, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the terrace region, first laterally isolated contact structures including a respective first contact via structure and a respective first dielectric spacer, and second laterally isolated contact structures including a respective second contact via structure and a respective second dielectric spacer. The respective first contact via structure contacts a top surface of a respective first electrically conductive layer in the respective step of the plurality of steps. The respective second contact via structure extends through the respective first electrically conductive layer in the respective step and contacts a top surface of a respective second electrically conductive layer which underlies the first electrically conductive layer in the respective step.