3D Memory Staircase Contacts With Stop Layers to Prevent Shorting
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Solution Overview
Problem
The challenge in three-dimensional memory fabrication is the tendency for higher gate layers to be penetrated through during the formation of contact posts, leading to shorting among different gate layers and poor performance due to the increased depth of contact holes and poor etching directionality, which complicates the process and reduces yield.
Innovation Solution
The introduction of a stack structure with alternating gate and dielectric layers, including first and second stops and a protection layer, allows for the formation of contact posts that avoid penetrating through the gate layers by etching to the stops, ensuring accurate contact with the gate layers and improving etching rate and linearity, thus preventing shorting and enhancing memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If contact holes are formed deeper to reach lower gate layers in 3D NAND structure, then electrical connection between contacts and gate layers is achieved, but etching directionality deteriorates and higher gate layers are penetrated through causing shorting
Solution Approach 1:
The patent introduces stop layers at predetermined positions within the dielectric layer before forming contact holes. These stop layers are prepared in advance to control the etching depth, preventing the etching process from penetrating through higher gate layers while still allowing access to lower gate layers. This preliminary placement of stop layers resolves the contradiction by providing depth control before the contact hole formation process begins.
Solution Approach 2:
The stop layers act as intermediary elements between the contact holes and the gate layers. They are positioned at specific depths to mediate the etching process, allowing contact holes to reach the intended gate layer while blocking further etching that would cause penetration through higher gate layers. This intermediary structure enables precise depth control and prevents shorting simultaneously.
2Ease of manufacture
If conventional contact hole formation process is used in 3D NAND, then fabrication process remains simple, but etching rate and linearity are poor leading to low yield
Solution Approach 1:
The patent segments the dielectric layer by introducing multiple stop layers at different depths, creating distinct etching stages. This segmentation allows the etching process to proceed in controlled steps with improved directionality and rate, while the overall fabrication process remains relatively simple. Each stop layer creates a defined etching boundary that enhances process control without significantly complicating the manufacturing flow.
Data Source
AI summary
The present disclosure provides a three-dimensional (3D) memory. The 3D memory may include a stack structure including gate layers and dielectric layers disposed alternately. The stack structure may include a step structure including a plurality of staircase structures disposed in a first direction and having different heights in a second direction. The 3D memory may include a plurality of first stops disposed in the first direction and located on the plurality of steps of at least one of the staircase structures, with each of the plurality of first stops disposed on the corresponding step of the plurality of steps. The 3D memory may include a protection layer covering the step structure and the first stops. The 3D memory may include a plurality of contact posts each extending through the protection layer and the first stop and being connected with the gate layer in the step corresponding to the first stop.