3D Memory Staircase Stop Structures for Stable Gate Replacement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, scaling becomes challenging and costly, and there is a need for increased memory density, which 3D memory architecture can address by stacking memory structures vertically, but it faces issues with structural support during the gate replacement process.
Innovation Solution
The introduction of different types of supporting structures and dummy channel structures to provide support during the gate replacement process, reducing stress and area consumption, and using etch-stop materials to maintain the stack structure integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and circuit design, then memory density increases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking memory structures vertically. This dimensional change allows continued scaling and density improvement without further reducing lateral feature sizes, thereby avoiding the exponential increase in manufacturing complexity and cost associated with advanced planar scaling
2Quantity of substance
If 3D memory architecture is implemented to increase memory density, then planar scaling limitations are overcome, but structural support issues arise during gate replacement process
Solution Approach 1:
The patent introduces supporting structures and dummy channel structures before the gate replacement process to provide preliminary structural support. These structures are formed in advance to prevent collapse of the vertical stack structure during subsequent processing steps, particularly during the removal of sacrificial layers and formation of conductive gate lines
Solution Approach 2:
The supporting structures and dummy channel structures act as intermediary elements that temporarily provide mechanical support during the gate replacement process. These intermediary structures are removed or integrated after serving their support function, enabling the complex gate replacement to proceed without compromising stack structure integrity
3Reliability
If supporting structures are added to maintain stack structure integrity during gate replacement, then structural stability improves, but area consumption increases
Solution Approach 1:
The patent places supporting structures and dummy channel structures selectively in specific regions of the memory array where they are most needed for structural support during gate replacement. Rather than uniformly distributing support structures across the entire array, the design optimizes their placement to provide local reinforcement at critical points, minimizing overall area consumption while maintaining necessary structural stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the costs and increases the yield rate of the gate replacement process in 3D memory devices by providing necessary structural support and minimizing area consumption.
Implementation Method 1
using etch-stop materials to maintain the stack structure integrity
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a semiconductor layer; a stack structure on the semiconductor layer, one or more stop structures, and second dielectric layers. The stack structure includes alternating conductive layers and first dielectric layers and has a core region and a staircase region adjacent to the core region. The one or more stop structures are in contact with the corresponding conductive layers and extend through the staircase region of the stack structure in a first direction toward the semiconductor layer. Each of the second dielectric layers is between two of the first dielectric layers. Each of the one or more stop structures is between one of the second dielectric layers and one of the conductive layers.