3D Memory Cell Structure With Straight Silicon Sidewalls
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in achieving high integration density and uniform electrical characteristics of memory cells due to non-uniform sidewall profiles of silicon patterns and word lines, which affect transistor performance.
Innovation Solution
The semiconductor device incorporates first and second pillar insulation patterns with specific alignment and silicon patterns having straight line sidewalls, along with word lines that extend in a direction perpendicular to these patterns, ensuring uniformity in silicon pattern width and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are developed with increased integration degree, then memory cell stacking in vertical direction is achieved, but non-uniform sidewall profiles of silicon patterns and word lines occur, affecting transistor performance
Solution Approach 1:
The device structure is segmented into distinct functional regions: silicon patterns forming transistor channels, pillar insulation patterns providing structural support and isolation, and word lines segmented into multiple layers for selective cell access. This segmentation allows each component to be optimized independently for both density and uniformity
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangements to three-dimensional vertical stacking. Memory cells are arranged in multiple layers along the vertical direction, with silicon patterns extending vertically and word lines wrapping around or contacting silicon patterns at different heights, achieving high integration density while maintaining controlled sidewall profiles through vertical geometry
2Quantity of substance
If silicon patterns are stacked vertically to increase integration, then memory capacity is improved, but uniform electrical characteristics of memory cells become difficult to maintain
Solution Approach 1:
Different regions of the device are given different properties: pillar insulation patterns provide mechanical support and electrical isolation in specific locations, silicon patterns are doped with specific impurity concentrations in controlled regions, and word lines are positioned at specific heights to create local electrical characteristics. This local optimization ensures uniform transistor performance across all vertically-stacked cells
Solution Approach 2:
The patent controls critical parameters including silicon pattern width, pillar insulation pattern dimensions, word line thickness and positioning, and impurity concentration profiles. By precisely controlling these parameters during fabrication, uniform electrical characteristics are maintained across all memory cells in the vertical stack
3Ease of operation
If word lines are configured to cross silicon patterns, then transistor control is achieved, but sidewall uniformity and electrical characteristics are affected
Solution Approach 1:
Word lines are configured to wrap around or contact silicon patterns with curved or rounded profiles rather than sharp angles. This curvature approach, particularly in vertically-stacked configurations, allows word lines to maintain electrical contact for transistor control while avoiding stress concentrations and maintaining uniform sidewall profiles of the silicon patterns
Data Source
AI summary
A semiconductor device may include first pillar insulation patterns on a substrate, second pillar insulation patterns on the substrate, silicon patterns stacked on the substrate to be spaced apart from each other in a vertical direction, a word line on each of upper and lower surfaces of each silicon pattern, a bit line contacting a first sidewall of at least a first silicon pattern of the silicon patterns, and a capacitor contacting a second sidewall of the first silicon pattern. Each of the first pillar insulation patterns may extend in the vertical direction from an upper surface of the substrate. The first pillar insulation patterns may be spaced apart from each other in a first direction, and may be aligned in a line. Each of the second pillar insulation patterns may extend in the vertical direction. The second pillar insulation patterns may be spaced apart from each other in the first direction, and may be aligned in a line. The second pillar insulation patterns and the first pillar insulation patterns may overlap with each other in a second direction perpendicular to the first direction. Each of the silicon patterns may extend in the second direction and be positioned between two first pillar insulation patterns and between two second pillar insulation patterns, and each of the silicon patterns may include two sidewalls opposite each other in the first direction and having a straight line shape. Each word line may extend in the first direction to cross the silicon patterns. Each word line may contact a sidewall of at least one insulation pattern of the first pillar insulation patterns and/or at least one insulation pattern of the second pillar insulation patterns. The bit line may extend in the vertical direction. The capacitor may be disposed in a horizontal direction to have a dielectric layer horizontally between a lower electrode and an upper electrode.