3D Nonvolatile Memory Strapping Common Source Regions
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in achieving high integration and high-speed data updating while maintaining a compact cell array structure, particularly in three-dimensional configurations.
Innovation Solution
The proposed nonvolatile memory device features a three-dimensional structure with conductive patterns arranged on a semiconductor substrate, including semiconductor patterns extending to sidewalls, common source regions, and impurity regions of different conductivity types, along with contact holes and plugs for electrical connections, allowing for efficient data storage and retrieval without increasing the cell array size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional structure is adopted to increase integration density, then the number of memory cells per unit area increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to a three-dimensional structure by stacking multiple conductive patterns (word lines, bit lines, selection lines) vertically. This allows memory cells to be arranged in multiple layers, significantly increasing integration density while maintaining a compact footprint on the semiconductor substrate.
Solution Approach 2:
The patent implements nested conductive patterns where word lines, bit lines, and selection lines are stacked vertically in a nested configuration. Each conductive pattern layer is positioned above the previous layer, creating a compact three-dimensional structure where multiple functional elements occupy overlapping vertical spaces, thereby increasing density without proportionally increasing device complexity.
2Ease of manufacture
If common source regions are electrically connected across separated cell arrays, then manufacturing efficiency improves, but the risk of interference between adjacent cell arrays increases
Solution Approach 1:
The patent introduces an insulating layer positioned between adjacent common source regions in separated cell arrays. This insulating layer acts as an intermediary that provides electrical isolation, preventing harmful interference between adjacent cell arrays while still allowing the common source regions to be formed in the same manufacturing step, thus maintaining manufacturing efficiency.
Solution Approach 2:
The patent divides the common source regions into separate, isolated segments for adjacent cell arrays by introducing insulating material between them. This segmentation electrically isolates the common source regions of different cell arrays, preventing interference while allowing simultaneous formation during manufacturing, thereby balancing manufacturing efficiency with electrical isolation.
Data Source
AI summary
Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.