3D Memory Gate Line Slit Plugs for Word Line Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As 3D memory devices scale with increasing oxide/nitride layers, the etch depth of gate line slits increases, leading to a risk of word line structure collapse due to stress, which affects subsequent fabrication processes like lithographic alignment, and existing solutions either increase manufacturing costs or fail to adequately reduce the risk of electrical leakage.
Innovation Solution
The method involves forming an alternating dielectric stack with structure strengthen plugs having a narrow support body and enlarged connecting portions, which are connected to the gate line slit structures, allowing for a thicker silicon oxide layer between the conductive wall and word line while minimizing the area of the structure strengthen plug, reducing the risk of electrical leakage and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of oxide/nitride layers is increased to improve area utilization, then the memory density is improved, but the etch depth of gate line slit increases resulting in word line structure collapse risk
Solution Approach 1:
The gate line slit is divided into multiple segments by forming intermediate connection structures that connect to the word line at different heights. This segmentation allows the gate line slit to maintain electrical connection while reducing stress concentration, preventing structure collapse even as etch depth increases with more oxide/nitride layers
Solution Approach 2:
The connection between gate line slit and word line is extended from a single-plane connection to a multi-dimensional structure with intermediate connection points at different heights. This vertical dimensionality addition distributes stress across multiple levels, preventing collapse while maintaining electrical connectivity
2Reliability
If a thicker silicon oxide layer is formed between conductive wall and word line to reduce electrical leakage, then the reliability is improved, but the manufacturing cost increases
Solution Approach 1:
The silicon oxide layer thickness is optimized locally at critical stress and electrical fields (such as at the intermediate connection points and word line interfaces) rather than uniformly throughout. This localized quality enhancement prevents electrical leakage at critical points while minimizing overall material usage and deposition cost
Data Source
Figure 1
Figure 2(A)~2(C)
Figure 3
AI summary
Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a top selective gate cut and two structure strengthen plugs in an upper portion of the alternating dielectric stack, wherein each structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a plurality of channel structures in the alternating dielectric stack; forming a plurality of gate line slits in the alternating dielectric stack, wherein each gate line slit exposes a sidewall of one enlarged connecting portion of a corresponding structure strengthen plug; transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug.