3D Memory Stack Layout for Stress and Pillar Alignment Control
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Solution Overview
Problem
Three-dimensional nonvolatile memory devices face challenges in managing stress generated by material differences between stacked structures and peripheral parts, leading to potential distortion and misalignment of pillars due to expansion and contraction, as well as risks of short-circuits and contamination during the dicing process.
Innovation Solution
The semiconductor memory device employs a stacked structure with stepped portions where some layers extend from the memory region to the peripheral circuit region, using insulating and conducting layers to manage stress and prevent short-circuits, while maintaining material differences to reduce distortion and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked structure with material differences is used to achieve three-dimensional nonvolatile memory, then memory capacity and integration are improved, but stress-induced distortion and misalignment of pillars occur due to expansion and contraction
Solution Approach 1:
The stacked structure is divided into multiple memory regions with different material compositions. Each memory region contains pillars with specific materials (e.g., silicon oxide, silicon nitride) that are segmented and arranged to create controlled stress distribution patterns, preventing uniform expansion/contraction-induced misalignment
Solution Approach 2:
Different regions of the stacked structure are assigned different material properties and stress characteristics. By locally varying the material composition and thickness of layers in different memory regions, the patent creates zones with complementary stress patterns that counterbalance each other, maintaining pillar alignment despite overall thermal and mechanical stress
2Reliability
If stacked structure layers are extended to peripheral parts, then stress management is improved, but device complexity increases due to additional insulating and conducting layers
Solution Approach 1:
The insulating and conducting layers that extend into peripheral parts serve multiple functions: they act as stress-relief structures, provide electrical isolation between memory regions and peripheral circuits, and maintain structural integrity. This multi-functionality reduces the need for separate dedicated stress-management components, offsetting the apparent complexity increase
Solution Approach 2:
The patent extends layers not only vertically (stacking direction) but also horizontally into peripheral regions, creating a three-dimensional stress distribution network. This dimensional extension allows stress to be managed across multiple spatial dimensions, improving reliability while the systematic layering approach keeps the complexity manageable through pattern repetition
3Manufacturing precision
If material differences are maintained in stacked structure, then stress-induced distortion is reduced, but risk of short-circuits and contamination during dicing increases
Solution Approach 1:
Insulating layers are introduced as intermediary structures between regions with different materials. These insulating layers act as barriers that prevent direct electrical contact between conductive elements in adjacent memory regions, eliminating short-circuit risks while allowing the underlying material differences to remain for stress management
Solution Approach 2:
The stacked structure includes pre-designed insulating and protective layers that are formed before the dicing process. These layers serve as cushioning barriers that prevent contamination and short-circuits during subsequent manufacturing steps, particularly during dicing when material differences could otherwise cause problematic stress-induced breakage or contamination
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a stacked structure including a plurality of first layers stacked with a second layer therebetween above a substrate having a memory region in which a plurality of memory cells are arranged and an outer edge portion surrounding the memory region, the stacked structure having a stepped portion at which ends of the first layers form a stepped shape at an end of the stacked structure in a first direction within the memory region, wherein at least some of the first layers among the plurality of first layers extend, along a second direction perpendicular to the first direction, from above the outer edge portion at a first end side of the substrate through above the memory region over the substrate to above the outer edge portion at a second end side of the substrate.