3D Nonvolatile Memory Strings for Compact High-Capacity Chips
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high integration and large capacity due to complex manufacturing processes, increased cost, and issues with three-dimensional memory cell structures, such as short circuits and variations in transistor properties, leading to larger cell areas and increased word line drivers.
Innovation Solution
A nonvolatile semiconductor memory device with a design featuring memory strings composed of pillar-shaped semiconductors surrounded by insulation films and electrodes, forming conductor layers in a two-dimensional spread, which simplifies manufacturing and reduces the need for complex processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell structures are used to increase integration degree, then memory capacity and integration are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell layouts to three-dimensional stacked memory cell structures. Multiple memory cell layers are vertically stacked above a common substrate, with word lines and bit lines extending through multiple levels. This dimensional change allows significantly higher memory capacity within the same footprint area while using standardized planar fabrication processes for each layer, thus improving capacity without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked vertically, with each layer containing memory cells formed within trenches or cavities of the layer below. The word lines and control gates are positioned in intermediate layers, effectively nesting functional elements within each other's spatial volume. This nested arrangement maximizes memory density by utilizing vertical space efficiently while maintaining manufacturability through sequential layer formation.
2Quantity of substance
If design rules are reduced to achieve further micro processing, then integration degree is improved, but processing technique quality requirements become excessively high
Solution Approach 1:
Instead of continuously reducing lateral design rules which demands ever-higher lithography precision, the patent achieves higher integration by stacking memory cells in the vertical dimension. The lateral dimensions can maintain relaxed design rules with standard manufacturing precision, while the vertical stacking provides the integration boost. This separates the integration challenge from the precision constraint.
Solution Approach 2:
The patent divides the memory structure into multiple discrete layers that can be fabricated separately using standard process steps. Each layer is formed with conventional precision requirements, and the overall high integration is achieved by combining multiple such layers. This segmentation allows each manufacturing step to operate within achievable precision limits while the cumulative structure achieves high integration.
3Device complexity
If simple stacking of memory cells is used, then manufacturing complexity is reduced, but cell area increases and cost benefits are lost
Solution Approach 1:
The patent resolves this contradiction by stacking memory cell layers vertically in the third dimension rather than expanding laterally in two dimensions. This vertical stacking achieves high memory capacity within a compact footprint, avoiding large cell area while maintaining manufacturing simplicity through repeated use of standard planar process steps for each layer.
Solution Approach 2:
The patent merges multiple memory cell layers into a single integrated three-dimensional structure sharing common substrate regions, word line structures, and control gate formations. This consolidation achieves high density without requiring separate large-area cells for each memory location, thereby reducing overall cell area while maintaining manufacturing efficiency through combined structure formation.
4Quantity of substance
If SGT structure transistors are used, then three-dimensional memory cell functionality is achieved, but short circuits between adjacent gates occur due to micro processing limitations
Solution Approach 1:
The patent positions control gates and word lines in vertically separated layers with adequate dielectric spacing between them, rather than having them adjacent in the same plane as in SGT structures. This vertical separation in three-dimensional space eliminates the short circuit risk between gates that plagues planar SGT designs, while still achieving three-dimensional memory functionality through the stacked cell architecture.
Solution Approach 2:
The patent introduces thick dielectric layers and isolation structures between adjacent gate elements and between memory cell layers. These intermediary dielectric materials provide electrical insulation and prevent short circuits between gates that would otherwise be in close proximity due to micro processing limitations, thereby ensuring reliability while maintaining the compact three-dimensional structure.
Data Source
AI summary
A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.