3D Memory Conductive Stripe Layout for Lower Middle-Level Resistance
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high storage capacity and efficient conductive stripe design, particularly in reducing resistance while maintaining structural integrity.
Innovation Solution
The proposed three-dimensional memory device features conductive stripes with varying thicknesses, where the middle-level conductive stripes have a larger thickness, forming an integral structure to reduce resistance, and includes a substrate, conductive stripes, pillar elements, and spacers to enhance electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all conductive stripes have the same thickness, then the manufacturing process is simple, but the resistance of middle-level conductive stripes is high
Solution Approach 1:
The patent applies local quality by making the thickness of conductive stripes position-dependent. Specifically, conductive stripes at middle levels (levels 2 to N-1) have a greater thickness than those at the first and last levels. This localized variation in geometric property directly addresses the high resistance issue in middle-level stripes without requiring complete redesign of the entire structure, thus improving electrical conductivity while maintaining reasonable manufacturing complexity.
Solution Approach 2:
The patent changes the geometric parameter (thickness) of conductive stripes based on their position in the three-dimensional array. By increasing the thickness parameter for middle-level conductive stripes, the resistance is reduced. This parameter change is implemented through a selective deposition or formation process that distinguishes between different level positions, achieving the desired electrical property optimization.
2Reliability
If middle-level conductive stripes have larger thickness, then resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the conductive stripe formation process into different stages or groups based on level position. Instead of forming all conductive stripes uniformly, the process is divided to create first-level stripes with one thickness, middle-level stripes with a greater thickness, and last-level stripes with the original thickness. This segmentation allows independent control of thickness parameters for each group, managing manufacturing precision requirements through process differentiation.
Solution Approach 2:
The patent introduces a new dimension of control by making conductive stripe thickness dependent on the vertical level position in the three-dimensional array. This creates a thickness gradient through the vertical dimension, where middle levels have increased thickness. By utilizing this vertical dimension for parameter variation, the patent achieves resistance reduction while distributing the manufacturing precision challenge across different process stages rather than requiring uniform precision throughout.
Data Source
AI summary
A memory device includes a substrate, a first conductive stripe disposed on the substrate and extending along a first direction, a second conductive stripe disposed on the first conductive stripe, a first pillar element and a spacer. The second conductive stripe extends along a second direction intersected with the first direction. A thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure. The first pillar element is disposed at an intersection between the first conductive stripe and the second conductive stripe, and extends from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction intersected with the first direction and the second direction. The first pillar element includes a switching layer and a memory layer corresponding to a first level.