3D Memory Sub-Array Layout Without Staircase Structures
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Solution Overview
Problem
Current 3D memory array architectures face challenges in maximizing cell density and chip area efficiency due to the presence of staircase structures and dummy memory cells, which affect the uniformity and performance of memory cells.
Innovation Solution
The proposed solution involves forming multiple 3D memory sub-arrays within a single tableland feature, eliminating staircase structures between sub-arrays and reducing the number of dummy memory cells, thereby optimizing chip area usage and enhancing memory cell performance by arranging sub-arrays in a manner that allows for efficient electrical isolation and uniform performance across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 3D memory array architecture with staircase structures is used, then manufacturing process is simplified, but cell density and chip area efficiency are reduced
Solution Approach 1:
The memory array is divided into multiple independent sub-arrays, each with its own bit lines and source lines. This segmentation allows each sub-array to be optimized independently, eliminating the need for staircase structures while maintaining overall array functionality and improving cell density.
Solution Approach 2:
The patent transitions from a two-dimensional memory array layout to a three-dimensional stacked architecture. Multiple memory layers are stacked vertically, with through-silicon vias (TSVs) providing vertical interconnects, thereby increasing storage capacity per unit area without requiring complex staircase structures.
2Area of stationary object
If staircase structures are eliminated and multiple sub-arrays are formed in a single tableland, then chip area efficiency is improved, but electrical isolation between sub-arrays becomes more challenging
Solution Approach 1:
Deep trench isolation structures filled with dielectric material are introduced as intermediaries between adjacent sub-arrays. These isolation trenches physically separate the bit lines and source lines of different sub-arrays, ensuring electrical isolation while allowing compact arrangement of multiple sub-arrays within a single tableland feature.
3Area of stationary object
If dummy memory cells are reduced, then chip area is optimized, but uniformity of memory cell performance may be affected
Solution Approach 1:
Different regions of the memory array are designed with locally optimized characteristics. Sub-arrays positioned at different locations within the tableland feature can have adjusted dimensions or configurations to compensate for variations in stress, temperature, or electrical characteristics, thereby maintaining uniform performance across the entire array while minimizing dummy cell requirements.
Data Source
AI summary
A 3D memory array includes a tableland feature formed with multiple 3D memory sub-arrays that are arranged in an X-axis direction. Each 3D memory sub-array includes multiple memory cells that are distributed in multiple columns arranged in the X-axis direction, multiple bit lines extending in a Z-axis direction, multiple source lines extending in the Z-axis direction, and multiple word lines extending in a Y-axis direction. Each memory cell includes a first electrode, a second electrode and a gate electrode. Each bit line interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction. Each bit line is electrically connected to another bit line of the same 3D memory sub-array, which is aligned with the bit line in the X-axis direction, and is electrically isolated from the bit lines of another 3D memory sub-array.