3D Nonvolatile Memory Sub-Divided Active Bars
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the high cost of advanced equipment required for fine pattern formation, and existing three-dimensional memory technologies face challenges in achieving uniform electrical characteristics and high integration density.
Innovation Solution
The method involves alternatingly stacking conductive and insulating layers on a substrate to form vertically stacked gates and active bars, with each active bar having a varying width along its height, and using gate dielectrics with charge storage layers to enhance memory cell performance and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional memory devices use advanced fine pattern forming technology to increase integration, then integration level improves, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Multiple memory cells are stacked along the vertical direction, allowing integration scaling without requiring finer lateral patterning. This dimensional change enables higher integration while avoiding the need for extremely expensive advanced lithography equipment.
2Ease of manufacture
If three-dimensional memory structures are formed with uniform active bars, then manufacturing simplicity is maintained, but electrical characteristic uniformity deteriorates due to process variations
Solution Approach 1:
The active bar is segmented into multiple sections along its length, with each section having a different width. This segmentation allows independent optimization of electrical characteristics in different regions. The varying width sections compensate for process variations and achieve uniform electrical characteristics while maintaining a manufacturable structure using standard fabrication processes.
3Reliability
If sub-divided active bars with varying width are used, then electrical characteristic uniformity improves, but device complexity increases
Solution Approach 1:
Multiple functional elements are merged into the active bar structure itself. The varying width sections serve both as electrical conduction paths and as means to control electrical characteristics. The gate structures are merged with the insulating layers to form integrated gate dielectric stacks. This merging achieves uniform electrical characteristics without requiring separate control mechanisms, thereby limiting the increase in device complexity.
Data Source
AI summary
Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.