3D Memory Substrate Bonding for Higher Density and Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data storage capacity and reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a first substrate structure with vertically stacked gate electrodes, a supporter layer, channel structures penetrating the gate electrodes, and separation regions. A second substrate structure with circuit elements and bonding metal layers is connected to the first substrate structure, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The device is divided into two separate substrate structures: a first substrate structure containing the three-dimensionally arranged memory cells for high-capacity storage, and a second substrate structure containing peripheral circuit elements. This segmentation allows each substrate to be optimized independently, reducing overall device complexity while maintaining high storage capacity through the vertical memory cell arrangement on the first substrate.
2Device complexity
If two substrate structures are connected through bonding to enhance integration, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
Bonding metal layers are introduced as intermediary elements between the first and second substrate structures. These metal layers facilitate the bonding process and provide tolerance for alignment variations, thereby reducing the stringent manufacturing precision requirements that would otherwise be necessary for direct substrate-to-substrate bonding.
3Quantity of substance
If vertically stacked gate electrodes are used to increase storage density, then storage capacity is improved, but manufacturing difficulty increases
Solution Approach 1:
The memory cells are arranged in a vertical three-dimensional configuration with stacked gate electrodes extending in the first direction, transitioning from traditional two-dimensional planar arrangement to three-dimensional vertical stacking. This dimensional change increases storage density by utilizing the vertical space above the substrate, allowing multiple memory cells to be stacked along the vertical axis.
Data Source
AI summary
A semiconductor device includes a first substrate structure, and a second substrate structure connected to the first substrate structure and including circuit elements and second bonding metal layers. The first substrate structure includes gate electrodes stacked along a first direction, a supporter layer on the gate electrodes, channel structures extending along the first direction while penetrating the gate electrodes, separation regions extending in the first direction and a second direction by penetrating through the gate electrodes, and first bonding metal layers connected to the second bonding metal layers. The separation regions respectively include first regions spaced apart from each other along the second direction and a second region surrounding side surfaces of the first regions and extending in the second direction. The first regions and the channel structures penetrate the supporter layer, and a portion of a lower surface of the supporter layer is in contact with the second region.