3D Semiconductor Memory With Substrate Contact Region
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Solution Overview
Problem
High-density three-dimensional semiconductor memory devices face challenges in reducing the area occupied by peripheral access circuitry, making it difficult to integrate memory arrays above the peripheral access circuit due to substrate constraints, especially in TCAT structures.
Innovation Solution
A three-dimensional semiconductor device design with a substrate contact formed in the middle of memory strings, featuring a common source region, channel layers, insulating layers, control gates, and bit line wiring, which reduces the area occupied by peripheral circuitry and enhances memory erase/write performance and storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory array is arranged two-dimensionally on the substrate, then the device structure is simple, but the integration density is limited and signal conflict increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional structure by forming vertical channel vias through the substrate and stacking multiple memory layers above the substrate surface. This dimensional change enables significantly higher integration density while maintaining manageable device complexity through systematic fabrication processes.
2Quantity of substance
If the peripheral access circuit area is reduced to increase memory density, then the storage capacity increases, but it becomes difficult to integrate memory arrays above the peripheral access circuit due to substrate constraints
Solution Approach 1:
The patent forms vertical channel vias that extend through the substrate and into the peripheral access circuit region, allowing memory strings to be positioned directly above peripheral circuits in the vertical dimension. This enables overlapping placement of memory arrays and peripheral circuits in different vertical layers, effectively increasing storage density without complicating the two-dimensional chip layout.
Solution Approach 2:
The patent implements a nested structure where memory strings are positioned within the vertical space above the peripheral access circuit region. The channel vias are formed through the substrate and extend into the peripheral circuit area, creating a nested arrangement where memory structures are embedded above the peripheral circuits, maximizing space utilization.
3Quantity of substance
If the channel via depth is increased to access the substrate surface, then the memory cell density improves, but the fabrication precision requirements increase
Solution Approach 1:
The patent segments the channel via formation process into multiple controlled steps: first forming openings through the substrate to a controlled depth, then selectively depositing materials in the openings, and finally forming additional openings if needed. This segmentation of the via formation process enables precise control over via depth and reduces the complexity of single-step deep etching, thereby maintaining manufacturing precision while achieving high memory cell density.
Data Source
AI summary
A three-dimensional semiconductor device includes: A peripheral circuit, distributed on a substrate; a plurality of memory cells above the peripheral circuit, each of which includes: a common source region, between the memory cell and the peripheral circuit; a channel layer, distributed in a direction perpendicular to the surface of the substrate; at least one substrate contact layer, extending horizontally from the central portion of the channel layer parallel to the surface of the substrate, each comprising at least one substrate contact region; a plurality of insulating layers, located on sidewalls of the channel layer; a plurality of control gates, sandwiched between adjacent insulating layers; a gate dielectric layer, located between the channel layer and the control gates; a drain region, located at top of the channel layer; a substrate contact lead-out line, electrically connected to the substrate contact regions; and a bit line wiring, electrically connected to the drain region of each memory cell and the peripheral circuit. The substrate contact regions are formed in the middle of the memory strings, improving the erase/write performance and reliability of the memory, increasing the density of the storage array, reducing the entire memory chip area and saving the costs.