3D Semiconductor Memory Support Pattern Layout for Higher Cell Density
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Solution Overview
Problem
The integration of two-dimensional or planar semiconductor devices is limited by the expensive equipment needed to create finer patterns, which restricts the increase in memory cell density and overall productivity.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate having peripheral circuit structures, stacked structures with gate electrodes, and a separation structure including support patterns with an internal insulating layer, allowing for increased density and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used to increase integration, then memory cell density can be improved, but expensive processing equipment is needed to create finer patterns which limits productivity and increases manufacturing cost
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction (first direction) on the substrate, enabling increased memory cell density without requiring finer lateral patterning. This dimensional change allows achieving high integration while avoiding the need for expensive fine-patterning equipment.
2Quantity of substance
If two-dimensional or planar semiconductor devices are used to increase integration, then memory cell density can be improved, but the expensive processing equipment needed restricts productivity
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent achieves higher memory cell density per unit area without requiring proportionally more expensive processing equipment. The vertical stacking approach allows standard patterning equipment to produce the necessary structures, thereby maintaining productivity while increasing density.
Solution Approach 2:
The memory device is segmented into multiple independent stacked memory cell structures that can be formed and processed separately. Each stacked structure contains multiple memory cells arranged vertically, allowing parallel processing and fabrication of multiple units simultaneously, which enhances manufacturing productivity.
3Quantity of substance
If three-dimensional stacked structures are implemented to increase density, then memory cell density improves, but device complexity increases
Solution Approach 1:
The patent employs vertical stacking of memory cells in the first direction, creating three-dimensional structures that increase density. The separation structure extends in the second direction to divide these stacked structures, providing a systematic approach to managing the complexity of three-dimensional arrangements while maintaining fabrication feasibility.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a plurality of peripheral circuit structures on a substrate, a plurality of stacked structures, each the plurality of stacked structures including a plurality of gate electrodes stacked on the plurality of peripheral circuit structure in a first direction perpendicular to a lower surface of the substrate, and the plurality of stacked structure being spaced apart from each other in a second direction parallel to the lower surface of the substrate, a separation structure extending between the plurality of stacked structures in a third direction intersecting the first direction and the second direction, the separation structure including a plurality of support patterns that are spaced apart from each other in the third direction in the separation structure; and an internal insulating layer surrounding a side surface of each of the plurality of support patterns.