3D Memory Supporting Structure for Staircase Region Integrity
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Solution Overview
Problem
In 3D NAND memory devices, the formation of slit structures for electrical connections introduces leakage current and parasitic capacitance, and the removal of sacrificial layers can cause stack structure collapse in the staircase region, leading to reduced production yield and electrical performance issues.
Innovation Solution
A supporting structure is introduced that overlaps the staircase region, made of a material different from the sacrificial layer, to prevent etching and maintain structural integrity during the formation of sidewall SEGs, thereby avoiding stack collapse and enhancing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sacrificial layers are removed to form slit structures for electrical connections, then electrical connectivity is improved, but stack structure collapse occurs in the staircase region
Solution Approach 1:
A supporting structure is formed in the staircase region before the sacrificial layer removal process. This supporting structure remains in place during etching to provide mechanical support to the stack structure, preventing collapse. After the slit structures are formed, the supporting structure is removed, having served its protective function throughout the critical fabrication steps.
Solution Approach 2:
The supporting structure acts as an intermediary element that temporarily replaces the sacrificial layer's structural role. It provides the necessary mechanical support during the etching process without interfering with the formation of electrical connections, and is subsequently removed to leave the final device structure.
2Reliability
If slit structures are formed for electrical connections, then electrical access is improved, but leakage current and parasitic capacitance increase
Solution Approach 1:
The supporting structure is selectively placed only in the staircase region where it is needed for structural support, while allowing the core array region to proceed with normal slit structure formation. This localized approach provides structural reinforcement where geometry is most vulnerable without adding unnecessary material that could create additional leakage paths or capacitance in the active memory regions.
3Productivity
If supporting structure is added to prevent stack collapse, then production yield is improved, but device complexity increases
Solution Approach 1:
The supporting structure is designed as a temporary, disposable element that is formed, serves its protective function during critical fabrication steps, and is then completely removed. It is not part of the final device structure, so while it adds temporary complexity to the fabrication process, it does not increase the complexity of the final product.
Solution Approach 2:
The supporting structure is intentionally designed to be discarded after serving its purpose. It is formed to prevent stack collapse during sacrificial layer removal, and then systematically removed in a subsequent step, leaving no trace in the final device. This approach trades temporary process complexity for permanent yield improvement.
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.