3D Memory Through-Array Contacts Without Barrier Structures

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Solution Overview

Problem

Planar memory cells face density limitations and increasing fabrication challenges as feature sizes approach a lower limit, making 3D memory architectures necessary to enhance memory density and reduce fabrication costs.

Innovation Solution

A 3D memory device design that eliminates barrier structures around through array contacts (TACs), allowing for reduced area usage and simplified fabrication processes, while maintaining functionality and increasing process margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If barrier structures are formed around through array contacts (TACs), then contact protection and isolation are improved, but device complexity and fabrication difficulty increase

Engineering Contradiction:

Improvecontact protectionVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the barrier structure that was previously formed around TACs, eliminating the complex multi-layer barrier formation process while maintaining acceptable contact protection through alternative means such as spacer structures and process control

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of adding barrier structures to protect TACs, the invention inverts the approach by using spacer structures and etch selectivity to provide protection, turning a protection-addition problem into a protection-through-omission solution

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If barrier structures are formed around through array contacts (TACs), then contact isolation is improved, but fabrication process complexity increases

Engineering Contradiction:

Improvecontact isolationVSAvoidfabrication process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent eliminates the barrier formation steps (deposition and etch of barrier layers) around TACs, simplifying the fabrication process while maintaining adequate isolation through spacer structures and selective etching processes

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The spacer structures automatically provide isolation functions that previously required separate barrier layers, allowing the same structural elements to serve multiple functions (mechanical support, isolation, and alignment reference)

Inventive Principle:

Principle #25Self-service

3Quantity of substance

If feature sizes of planar memory cells are scaled down, then memory density is improved, but fabrication challenges and costs increase

Engineering Contradiction:

Improvememory densityVSAvoidfabrication process

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from planar memory cell scaling to 3D vertical channel structures, moving the density improvement strategy from lateral dimension scaling to vertical dimension exploitation, thereby avoiding the fabrication challenges associated with continued planar scaling

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Reliability

If through array contacts (TACs) use barrier structures, then contact reliability is improved, but area usage increases

Engineering Contradiction:

Improvecontact reliabilityVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the barrier structures around TACs, reducing the lateral footprint of contact regions and enabling higher contact density per unit area while maintaining adequate reliability through alternative protection mechanisms

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design increases memory cell density, decreases process costs, and improves fabrication extendibility by simplifying the fabrication flow for both current and future generations of 3D memory devices.

Implementation Method 1

A through array contact (TAC) extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS20250359048A1Three-dimensional memory devices having through array contacts and methods for forming the same

Publication Date: 2025.11.20 YANGTZE MEMORY TECH CO LTD

AI summary

In certain aspects, a semiconductor device includes a stack structure including conductive layers and dielectric layers that are interleaved in a first direction, and a first connection structure extending through the stack structure. The first connection structure has a circular cross-section in a plane perpendicular to the first direction. The first connection structure includes a first conductor layer and a first dielectric spacer over a sidewall of the first conductor layer. The first connection structure is connected to a peripheral device.